CY7C419-10JCT Cypress Semiconductor Corp, CY7C419-10JCT Datasheet
CY7C419-10JCT
Specifications of CY7C419-10JCT
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CY7C419-10JCT Summary of contents
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... FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH during retransmit, and then R is used to access the data. The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425, CY7C428, CY7C429, CY7C432, and CY7C433 are fabricated using an advanced 0.65-micron P-well CMOS technology. Input ESD protection is greater than 2000V and latch up is prevented by careful layout and guard rings ...
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... DATA OUTPUTS (Q 0 – READ CONTROL FLAG EF LOGIC FF EXPANSION LOGIC XO/HF Figure 2. 28-Pin DIP (Top View 7C419 FL/RT 0 7C420 7C424/5 MR 7C428 7C432 XO/ GND R CY7C419/21/25/29/33 MR RESET LOGIC FL/RT Figure 3. 32-PIn TQFP (Top View) 32 3130 7C419 7C421/5 7C433 Page FL/ XO/ [+] Feedback [+] Feedback [+] Feedback ...
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... CC [ Max GND CC OUT –10 Test Conditions Min Max = Max., Commercial Industrial MAX = Max., Commercial Commercial 10 Min. Industrial Commercial 5 –0.2V Industrial CY7C419/21/25/29/33 [2] Ambient Temperature V CC ° ° 5V ± 10 ° ° 5V ± 10% – +85 C All Speed Grades Min Max 2.4 0 [4] 0.8 – ...
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... Max., Commercial Industrial OUT MAX V = Max., Commercial OUT MHz All Inputs = Commercial V Min. Industrial IH All Inputs > Commercial V –0.2V Industrial CC Description Test Conditions Input Capacitance 4.5V Output Capacitance CC CY7C419/21/25/29/33 –40 –65 Max Min Max Min Max Max Unit ° MHz Page Unit ...
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... AC Test Load and Waveforms. HZR DVR Document #: 38-06001 Rev. *D –10 Min Max Min and –200 mV from transition is measured at the 1.5V level DVR CY7C419/21/25/29/33 –15 –20 –25 Max Min Max Min Max ...
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... Effective Read Pulse Width After EF HIGH RPE t Effective Write from Read HIGH WAF t Effective Write Pulse Width After FF HIGH WPF t Expansion Out LOW Delay from Clock XOL t Expansion Out HIGH Delay from Clock XOH Document #: 38-06001 Rev. *D CY7C419/21/25/29/33 –30 –40 Min Max Min Max Min ...
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... Figure 4. Asynchronous Read and Write DVR DATA VALID DATA VALID DATA VALID Figure 5. Master Reset [11] t MRSC t PMR t RPW t WPW t t RMR EFL t HFH t FFH Figure 6. Half-full Flag HALF FULL+1 t WHF CY7C419/21/25/29/33 t HZR DATA VALID HALF FULL t RHF Page [+] Feedback [+] Feedback [+] Feedback ...
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... EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid RTC PRT RTR Document #: 38-06001 Rev. *D ADDITIONAL FIRST READ READS t RFF ADDITIONAL FIRST WRITE WRITES t WEF [12] Figure 9. Retransmit [13] t RTC PRT t RTR CY7C419/21/25/29/33 FIRST WRITE FIRST READ VALID . RTC Page [+] Feedback [+] Feedback [+] Feedback ...
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... DATA OUT Figure 11. Full Flag and Write Data Flow-through Mode DATA DATA OUT DATA VALID Document #: 38-06001 Rev RAE t RPE t REF t t WEF A t HWZ DATA VALID t t WAF WPF t t RFF WFF DATA VALID t SD CY7C419/21/25/29/ Page [+] Feedback [+] Feedback [+] Feedback ...
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... Expansion In of device 2 (XI 1 Document #: 38-06001 Rev. *D Figure 12. Expansion Timing Diagrams WRITE TO FIRST PHYSICAL LOCATION OF DEVICE XOH DATA VALID READ FROM FIRST PHYSICAL LOCATION OF DEVICE XOH t DVR DATA VALID CY7C419/21/25/29/ DATA VALID t HZR t DVR DATA VALID Page [+] Feedback [+] Feedback [+] Feedback ...
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... Consequently, any depth or width FIFO can be created of word widths in increments of 9. When expanding in depth, a composite FF must be created by ORing the FFs together. Likewise, a composite EF is created by ORing the EFs together. HF and RT functions are not available in depth expansion mode. CY7C419/21/25/29/ are in a high impedance condition 0 8 after a valid write ...
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... Figure 13. Depth Expansion CY7C419 9 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432 CY7C419 9 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432 CY7C419 9 CY7C420/1 CY7C424/5 CY7C428/9 CY7C432 FIRST DEVICE CY7C419/21/25/29/ EMPTY Page [+] Feedback [+] Feedback [+] Feedback ...
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... Molded SOJ 51-85002 32-Pin Plastic Leaded Chip Carrier 51-85002 32-Pin Plastic Leaded Chip Carrier 51-85014 28-Pin (300-Mil) Molded DIP 51-85031 28-Pin (300-Mil) Molded SOJ 51-85002 32-Pin Plastic Leaded Chip Carrier CY7C419/21/25/29/33 Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial ...
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... Package Diagrams Figure 14. 32-Pin Thin Plastic Quad Flat Pack, 51-85063 Figure 15. 32-Pin Plastic Leaded Chip Carrier, 51-85002 Document #: 38-06001 Rev. *D CY7C419/21/25/29/33 51-85063-*B 51-85002-*B Page [+] Feedback [+] Feedback [+] Feedback ...
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... LEAD END OPTION MIN. MAX. PIN 0.291 0.330 0.300 0.350 28 SEATING PLANE 0.120 0.140 0.004 0.025 MIN. CY7C419/21/25/29/33 DIMENSIONS IN INCHES [MM] MIN. MAX. REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 0.290[7.36] 0.325[8.25] 0.009[0.23] 3° MIN. 0.012[0.30] 0.310[7.87] 0.385[9.78] 51-85014-*D A DETAIL EXTERNAL LEAD DESIGN ...
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... CY7C429–10AXC, CY7C429–15JXC, CY7C429–20JXC, CY7C433–10AXC, CY7C433–10JXC, CY7C433–15JXC, CY7C433–20AXC, CY7C433–20JXC 12/17/08 Added CY7C421-20JXI Removed CY7C419/25/29/33 from the ordering information table Removed 26-Lead CerDIP, 32-Lead RLCC, 28-Lead molded DIP packages from the data sheet Removed Military Information 06/04/2009 Corrected defective Logic Block diagram, Pinouts, and Package diagrams psoc ...