M25PE80-VMN6P NUMONYX, M25PE80-VMN6P Datasheet - Page 46

• Manufacturer Part Number: M25PE80-VMN6P
• Description: Flash Mem Serial-SPI 3.3V 8M-Bit 1M x 8 8ns 8-Pin SOIC N Tray
• Manufacturer: NUMONYX

Specifications of M25PE80-VMN6P

• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 4096
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Compliant

Power-up and power-down
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Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V
power on reset (POR) threshold voltage, V
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page write (PW), page program (PP),
page erase (PE), sector erase (SE), bulk erase (BE) and write to lock register (WRLR)
instructions until a time delay of t
the V
time, V
until the later of:
These values are specified in
If the delay, t
selected for read instructions even if the t
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the power-up and power-down phases.
At power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
Each device in a system should have the V
the package pins (generally, this capacitor is of the order of 0.1 µF).
At power-down, when V
(POR) threshold voltage, V
to any instruction. The designer needs to be aware that if a power-down occurs while a
write, program or erase cycle is in progress, some data corruption can result.
V
V
t
t
The device is in the standby mode (not the deep power-down mode).
The write enable latch (WEL) bit is reset.
WI
PUW
VSL
CC
SS
CC
threshold. However, the correct operation of the device is not guaranteed if, by this
(min) at power-up, and then for a further delay of t
at power-down
after V
is still below V
after V
VSL
, has elapsed, after V
CC
CC
passed the V
passed the V
CC
CC
WI
(min). No write, program or erase instructions should be sent
drops from the operating voltage, to below the power on reset
, all operations are disabled and the device does not respond
Table
CC
CC
PUW
) until V
WI
Section 3: SPI
(min) level
14.
threshold
CC
has elapsed after the moment that V
has risen above V
CC
PUW
WI
CC
reaches the correct value:
– all operations are disabled, and the device
rail decoupled by a suitable capacitor close to
delay is not yet fully elapsed.
modes.
VSL
CC
(min), the device can be
CC
CC
is less than the
rises above
CC
supply.
M25PE80