SLATA8GM1U STEC, SLATA8GM1U Datasheet - Page 8

• Manufacturer Part Number: SLATA8GM1U
• Manufacturer: STEC
• Type: PC Cardr

Specifications of SLATA8GM1U

• Density: 8GByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Package Type: Not Required
• Mounting: Socket
• Pin Count: 68
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3.18/4.75V
• Operating Supply Voltage (max): 3.465/5.25V
• Programmable: Yes
• Lead Free Status / RoHS Status: Compliant

SLATAxxx(M/G)M1U(I)
Datasheet
-REG
(PC Card I/O Mode)
-DMACK (not used for part
numbers with P)
(True IDE Mode)
WP
(PC Card Memory Mode)
Write Protect
-IOIS16
(PC Card I/O Mode)
-IOCS16
(True IDE Mode)
-INPACK
(PC Card Memory Mode)
-INPACK
(PC Card I/O Mode)
Input Acknowledge
DMARQ (Not used for part
numbers with P)
(True IDE Mode)
BVD1
(PC Card Memory Mode)
-STSCHG
(PC Card I/O Mode)
Status Changed
-PDIAG
(True IDE Mode)
-WAIT
(PC Card Memory Mode)
-WAIT
(PC Card I/O Mode)
IORDY
(True IDE Mode)
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
VCC
(PC Card Memory Mode)
VCC
(PC Card I/O Mode)
VCC
(True IDE Mode)
RESET
(PC Card Memory Mode)
Signal Name
Type
GND
VCC
I/O
O
O
O
I
1, 34, 35,
Number
61000-04497-117, April 2008
17, 51
Pin
33
60
63
59
68
58
The signal must also be active (low) during I/O Cycles when
the I/O address is on the bus.
In True IDE Mode this input signal is used by host in
response to DMARQ to initiate DMA transfers.
The ATA PC Card does not have a write protect switch;
therefore, this signal is held low after the completion of the
reset initialization sequence.
A low signal indicates that a 16 bit or odd byte only operation
can be performed at the addressed port.
Not defined in IDE Mode.
This signal is not used in this mode.
The Input Acknowledge signal is asserted by the ATA PC
Card when it is selected and responding to an I/O read cycle
at the address that is on the bus. The host uses this signal to
control the enable of any input data buffers between the ATA
PC Card and the host’s CPU.
In True IDE Mode this signal is asserted by the ATA PC Card
when it is ready to transfer data to/from the host. Data
direction is controlled by -IORD and -IOWR. This signal is
used in a handshake manner with -DMACK.
This signal is asserted high as since a battery is not used
with this product.
This signal is asserted low to alert the host to changes in the
RDY/-BSY and Write Protect states. Its use is controlled by
the Configuration and Status Register.
In True IDE Mode, this input/output signal is the Pass
Diagnostic signal in the Master/Slave handshake protocol.
This signal is not used by the ATA PC Card, and is pulled up
to VCC through a 4.7K ohm resistor.
This signal is not used by the ATA PC Card, and is pulled up
to VCC through a 4.7K ohm resistor.
This signal is not used by the ATA PC Card, and is pulled up
to VCC through a 4.7K ohm resistor.
Ground
Ground
Ground
+5 V or 3.3V power
+5 V or 3.3V power
+5 V or 3.3V power
When RESET is high, this signal resets the ATA PC Card. The
ATA PC Card is reset only at power up if this signal is left high or
open from power-up. The ATA PC Card can also be reset when
the soft reset bit in the Configuration Option Register is set.
Description
ATA PC Card
8