IS66WV51216DBLL-70TLI ISSI, Integrated Silicon Solution Inc, IS66WV51216DBLL-70TLI Datasheet

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IS66WV51216DBLL-70TLI

Manufacturer Part Number
IS66WV51216DBLL-70TLI
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS66WV51216DBLL-70TLI

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IS66WV51216DALL
IS66WV51216DBLL
8Mb LOW VOLTAGE, 
ULTRA LOW POWER PSEUDO CMOS STATIC RAM   
      
FEATURES
• High-speed access time:
• CMOS low power operation
• Single power supply
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00C
02/22/2011
– 70ns (IS66WV51216DALL/DBLL)
– 55ns (IS66WV51216DBLL)
– V
– V
dd
dd
     
= 1.7V - 1.95V (IS66WV51216dALL)
= 2.5V - 3.6V (IS66WV51216dBLL)
Lower Byte
Upper Byte
I/O8-I/O15
I/O0-I/O7
A0-A18
V
GND
DD
CS2
CS1
WE
OE
UB
LB
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
8M bit static RAMs organized as 512K words by 16
bits. It is fabricated using
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS66WV51216DALL/DBLL is packaged in the JEDEC
standard 48-ball mini BGA (6mm x 8mm) and 44-Pin TSOP
(TYPE II). The device is aslo available for die sales.
ISSI
MEMORY ARRAY
IS66WV51216DALL/DBLL is a high-speed,
COLUMN I/O
512K x 16
PRELIMINARY INFORMATION
ISSI
MARCH 2011
's high-performance
1

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IS66WV51216DBLL-70TLI Summary of contents

Page 1

... CMOS low power operation • Single power supply – 1.7V - 1.95V (IS66WV51216dALL) dd – 2.5V - 3.6V (IS66WV51216dBLL) dd • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Lead-free available FUNCTIONAL BLOCK DIAGRAM ...

Page 2

... IS66WV51216DALL IS66WV51216DBLL PIN CONFIGURATIONS: 48-Ball mini BGA (6mm x 8mm I CS1 8 C I/O I GND I/O A17 A7 I I/O V I/O NC A16 I/O A14 A15 I/O I I/O NC A12 A13 15 H A18 A10 A8 A9 PIN DESCRIPTIONS A0-A18 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 ...

Page 3

... IS66WV51216DALL IS66WV51216DBLL TRUTH TABLE         Mode  WE  CS1  CS2    Not Selected Output Disabled Read Write Note: CS2 input signal pin is only available for 48-ball mini BGA package parts. CS2 input is internally enabled for 44-pin TSOP-II pack- age parts. OPERATING  ...

Page 4

... IS66WV51216DALL IS66WV51216DBLL ABSOLUTE MAXIMUM RATINGS   Symbol  Parameter    V Terminal Voltage with Respect to GND term t Temperature Under Bias BIAS V V Related to GND Storage Temperature Stg P Power Dissipation t Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 5

... IS66WV51216DALL IS66WV51216DBLL CAPACITANCE (1)   Symbol  Parameter    c Input Capacitance In c Input/Output Capacitance out Note: 1. Tested initially and after any design or process changes that may affect these parameters. AC TEST CONDITIONS   Parameter        Input Pulse Level Input Rise and Fall Times ...

Page 6

... IS66WV51216DALL IS66WV51216DBLL 1.7V-1.95V POWER SUPPLY CHARACTERISTICS  Symbol  Parameter  Test Conditions          Dynamic Operating Supply Current I out All Inputs 0. Operating Supply Current CS2 = V I TTL Standby Current (TTL Inputs CS1 =     OR ULB Control V dd ...

Page 7

... IS66WV51216DALL IS66WV51216DBLL 2.5V-3.6V POWER SUPPLY CHARACTERISTICS  Symbol  Parameter  Test Conditions          Dynamic Operating Supply Current I out All Inputs 0. Operating Supply Current CS2 = V I TTL Standby Current (TTL Inputs CS1 =     OR ULB Control V dd ...

Page 8

... IS66WV51216DALL IS66WV51216DBLL READ CYCLE SWITCHING CHARACTERISTICS     Symbol  Parameter  t Read Cycle Time rc t Address Access Time AA t Output Hold Time oHA t t CS1/CS2 Access Time AcS1/ AcS2 t OE Access Time doe t ( High-Z Output Hzoe Low-Z Output (2) Lzoe t t CS1/CS2 to High-Z Output ...

Page 9

... IS66WV51216DALL IS66WV51216DBLL AC WAVEFORMS READ CYCLE NO. 2 (1,3) (CS1, CS2, OE, AND UB/LB Controlled) ADDRESS OE CS1 CS2 DOUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB Address is valid prior to or coincident with CS1 LOW transition. Integrated Silicon Solution, Inc. — www.issi.com Rev.  ...

Page 10

... IS66WV51216DALL IS66WV51216DBLL WRITE CYCLE SWITCHING CHARACTERISTICS     Symbol  Parameter  t Write Cycle Time CS1/CS2 to Write End ScS1/ ScS2 t Address Setup Time to Write End AW t Address Hold from Write End HA t Address Setup Time SA t LB, UB Valid to End of Write PWB ...

Page 11

... IS66WV51216DALL IS66WV51216DBLL WRITE CYCLE NO. 2  (WE Controlled HIGH During Write Cycle) ADDRESS OE CS1 CS2 WE LB, UB DOUT DIN WRITE CYCLE NO. 3  (WE Controlled LOW During Write Cycle) ADDRESS OE CS1 CS2 WE LB, UB DOUT DIN Integrated Silicon Solution, Inc. — www.issi.com Rev.  00C ...

Page 12

... IS66WV51216DALL IS66WV51216DBLL WRITE CYCLE NO. 4  (UB/LB Controlled) ADDRESS OE LOW CS1 HIGH CS2 WE UB HZWE D OUT DATA UNDEFINED ADDRESS 1 ADDRESS PWB WORD 1 HIGH DATA IN VALID Integrated Silicon Solution, Inc. — www.issi.com PWB WORD 2 t LZWE t HD DATA IN VALID UB_CSWR4.eps Rev.  00C ...

Page 13

... IS66WV51216DALL IS66WV51216DBLL Please avoid address change for less than t work around solution for this issue. Integrated Silicon Solution, Inc. — www.issi.com Rev.  00C 02/22/2011 during the cycle time longer than 15 ms (Figure 1). Figure 2 & 3 provide rc 13 ...

Page 14

... Industrial Range: -40°C to +85°C  Voltage Range: 2.5V to 3.6V    S peed (ns)  Order Part No.  55 IS66WV51216DBLL-55TLI IS66WV51216DBLL-55BLI 70 IS66WV51216DBLL-70TLI IS66WV51216DBLL-70BLI 14 Package TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free Package TSOP-II, Lead-free mini BGA (6mm x 8mm), Lead-free ...

Page 15

... IS66WV51216DALL IS66WV51216DBLL Integrated Silicon Solution, Inc. — www.issi.com Rev.  00C 02/22/2011 15 ...

Page 16

... IS66WV51216DALL IS66WV51216DBLL 16 Integrated Silicon Solution, Inc. — www.issi.com Rev.  00C 02/22/2011 ...

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