SR176A4T1GE STMicroelectronics, SR176A4T1GE Datasheet - Page 11

• Manufacturer Part Number: SR176A4T1GE
• Manufacturer: STMicroelectronics

Specifications of SR176A4T1GE

• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

SR176
3.9
Figure 10. Example of a complete transmission frame
3.10
Sent by the
Sent by the
Reader
SR176
Transmission frame
Between the Request and the Answer data transfer, there is a guard time without ASK and
BPSK modulation, for a minimum period of t
from transmission to reception mode, and is applied after each frame. After t
13.56 MHz carrier frequency is modulated by the SR176 at 847.5 kHz for a period of
t
by the SR176 represent the start bit (‘0’) of the Answer SOF. After the falling edge of the
Answer EOF, the reader has to wait for the minimum delay, t
Request Frame to the SR176.
CRC
The 16-bit CRC that is used by the SR176 follows the ISO 14443 Type B recommendation.
For further information, see
A two-byte CRC is appended to each Request and each Answer, within each frame, before
the EOF. The CRC is calculated on all the Bytes after the SOF, up to the CRC field.
On reception of a Request from a reader, the SR176 verifies that the CRC value is valid. If it
is invalid, it discards the frame and does not answer the reader.
On reception of an Answer from the SR176, it is recommended that the reader verify that the
CRC value is valid. If it is invalid, that choice of actions that are to be performed are the
responsibility of the reader designer.
The CRC is transmitted least significant byte first. Each byte is transmitted least significant
bit first.
Figure 11. CRC transmission rules
1
106kb/s
= 128/f
LSbit
SOF
bits
12
at
Input Data Transfer using ASK
Cmd
S
bits
10
, to allow the reader to synchronize. After t
Data
bits
10
t DR
CRC 16 (8 bits)
CRC
bits
LSByte
10
CRC
bits
10
Appendix
EOF
bits
10
128/f S
A. The initial register content is all ones: FFFFh.
t 0
MSbit
0
f S =847.5kHz
=128/f
128/f S
Output Data Transfer using 847kHz BPSK
LSbit
Sy
t 1
n
c
S
SOF
. This delay allows the reader to switch
1
bits
, the first phase transition generated
12
Data CRC CRC
bits
10
2
, before sending a new
CRC 16 (8 bits)
bits
10
MSByte
bits
10
EO F
bits
12
t 2
0
, the
Data transfer
SOF
ai07667
AI09060
MSbit
11/35