MT45V256KW16PEGA-70 WT Micron Technology Inc, MT45V256KW16PEGA-70 WT Datasheet - Page 9

• Manufacturer Part Number: MT45V256KW16PEGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45V256KW16PEGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef832450a3/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN
Power-Up Initialization Timing
In general, MT45V256KW16PE devices are high-density alternatives to SRAM and
PSRAM products that are popular in low-power, portable applications.
MT45V256KW16PE devices contain an 4,194,304-bit DRAM core organized as 262,144
addresses by 16 bits. These devices include the industry-standard, asynchronous
memory interface found on other low-power SRAM or PSRAM offerings.
Page mode access is also supported as a bandwidth-enhancing extension to the asyn-
chronous read protocol.
Micron PSRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. Initialization will load the CR with its default setting.
V
1.7V, the device will require 150µs to complete its self-initialization process (see
Figure 4). During the initialization period, CE# should remain HIGH. When initialization
is complete, the device is ready for normal operation.
Vcc, VccQ = 2.7V
The MT45V256KW16PE PSRAM product incorporates the industry-standard, asynchro-
nous interface. This bus interface supports asynchronous READ and WRITE operations
as well as page mode READ operation for enhanced bandwidth. The supported interface
is defined by the value loaded into the CR.
Micron PSRAM products power up in the asynchronous operating mode. This mode
uses the industry-standard SRAM control interface (CE#, OE#, WE#, and LB#/UB#).
READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping
WE# HIGH (see Figure 5 on page 10). Valid data will be driven out of the I/Os after the
specified access time has elapsed. WRITE operations occur when CE#, WE#, and LB#/
UB# are driven LOW (see Figure 6 on page 10). During WRITE operations, the level of
OE# is a “Don’t Care”; WE# overrides OE#. The data to be written is latched on the rising
edge of CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW time must be limited to
t
CEM.
CC
and V
CC
Q must be applied simultaneously, and when they reach a stable level above
4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16
t PU
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
normal operation
Device ready for
Vcc (MIN)
Functional Description
©2007 Micron Technology, Inc. All rights reserved.