STK10C68K55M Cypress Semiconductor Corp, STK10C68K55M Datasheet - Page 9

• Manufacturer Part Number: STK10C68K55M
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK10C68K55M

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 55ns
• Operating Supply Voltage (typ): 5V
• Package Type: CDIP
• Operating Temperature Classification: Military
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -55C to 125C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Not Compliant

March 2006
If the STK10C68 is in a
power-up
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
HARDWARE PROTECT
The STK10C68 offers two levels of protection to
suppress inadvertent
signals (E, G, W and NE) remain in the
dition at the end of a
STORE
RECALL
any one of these signals to the required state. In
addition to multi-trigger protection,
inhibited when V
against inadvertent
CC
or between E and system V
100
80
60
40
20
) will be initiated only after a transition on
cycle will not be started. The
0
RECALL
Figure 2: I
50
, the
CC
STORE
STORE
Cycle Time (ns)
SRAM
is below 4.0V, protecting
CC
100
WRITE
(max) Reads
STORE
s.
data will be corrupted.
cycles. If the control
150
CC
state at the end of
.
cycle, a second
TTL
CMOS
STORE
200
STORE
STORE
s are
con-
(or
9
LOW AVERAGE ACTIVE POWER
The STK10C68 draws significantly less current
when it is cycled at times longer than 55ns. Figure 2
shows the relationship between I
time. Worst-case current consumption is shown for
both
perature range, V
chip enable). Figure 3 shows the same relationship
for
less than 100%, only standby current is drawn
when the chip is disabled. The overall average cur-
rent drawn by the STK10C68 depends on the fol-
lowing items: 1)
duty cycle of chip enable; 3) the overall cycle rate
for accesses; 4) the ratio of
the operating temperature; 6) the V
O loading.
WRITE
Document Control # ML0006 rev 0.2
CMOS
100
80
60
40
20
0
cycles. If the chip enable duty cycle is
and
Figure 3: I
TTL
CMOS
50
CC
input levels (commercial tem-
= 5.5V, 100% duty cycle on
Cycle Time (ns)
CC
vs.
100
(max) Writes
TTL
READ
150
input levels; 2) the
CC
TTL
CMOS
CC
s to
and
STK10C68
level; and 7) I/
200
READ
WRITE
cycle
s; 5)