CY7C265-18WMB Cypress Semiconductor Corp, CY7C265-18WMB Datasheet - Page 6

• Manufacturer Part Number: CY7C265-18WMB
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C265-18WMB

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-04012 Rev. *B
respect to power-up and power-down during intelligent
programming also apply during architecture programming.
Once the supervoltages have been established and the
correct logic states exist on the other device pins,
Table 1. Mode Selection
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
Program Verify
Program Inhibit
Program Synchronous Enable
Program Initialize
Program Initial Byte
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
Program Verify
Program Inhibit
Program Synchronous Enable
Program Initialize
Program Initial Byte
Mode
Mode
Read or Output Disable
Read or Output Disable
Other
Other
V
V
V
A
A
V
A
A
A
A
A
A
V
A
A
A
A
A
A
A
A
A
PP
PP
PP
1
1
1
1
1
1
IHP
1
1
ILP
12
12
12
12
12
12
12
12
12
V
V
V
A
A
A
A
A
A
A
A
IHP
ILP
ILP
0
0
0
0
0
0
0
0
V
V
V
A
A
A
A
A
A
A
A
IHP
IHP
ILP
11
11
11
11
11
11
11
11
programming may begin. Programming is accomplished by
pulling PGM from HIGH to LOW and then back to HIGH with
a pulse width equal to 10 ms.
GND
PGM
GND
GND
GND
V
V
V
V
V
V
IHP
IHP
ILP
ILP
ILP
ILP
A
A
A
A
A
A
A
A
A
A
A
10
10
10
10
10
10
10
10
10
10
10
–A
–A
–A
–A
–A
–A
–A
–A
–A
–A
– A
V
CLK
CLK
7
7
7
7
7
7
7
7
7
7
V
V
V
V
V
V
IL
7
V
V
ILP
ILP
ILP
ILP
ILP
ILP
/V
Pin Function
Pin Function
IL
IL
IH
V
V
V
A
A
A
A
A
A
A
A
IHP
IHP
IHP
6
6
6
6
6
6
6
6
GND
GND
GND
GND
V
V
V
V
V
VFY
V
IHP
IHP
IHP
IHP
IHP
ILP
V
V
V
A
A
A
A
A
A
A
A
PP
PP
PP
5
5
5
5
5
5
5
5
V
V
V
V
V
V
V
E, I
V
V
V
A
A
A
A
A
A
A
A
A
A
A
PP
PP
PP
PP
PP
PP
PP
IL
IL
IL
4
4
4
4
4
4
4
4
4
4
4
–A
–A
–A
–A
–A
–A
–A
–A
–A
–A
–A
CY7C265
3
3
3
3
3
3
3
3
3
3
3
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O
O
O
O
O
High Z
D
D
D
D
D
7
7
7
7
7
7
7
7
7
7
V
–O
–D
–O
–O
–O
–D
–O
–D
–D
–D
V
V
A
A
A
A
A
A
A
A
IHP
ILP
ILP
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0