5962-88636033X Cypress Semiconductor Corp, 5962-88636033X Datasheet

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5962-88636033X

Manufacturer Part Number
5962-88636033X
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of 5962-88636033X

Lead Free Status / RoHS Status
Not Compliant
Features
Selection Guide
Cypress Semiconductor Corporation
Document #: 38-04002 Rev. *B
Minimum Address Set-Up Time
Maximum Clock to Output
Maximum Operating
Current
• CMOS for optimum speed/power
• High speed
• Low power
• Synchronous and asynchronous output enables
• On-chip edge-triggered registers
• Programmable asynchronous registers (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP or 28-pin
• 5V 10% V
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
LCC and PLCC
Logic Block Diagram
— 25 ns address set-up
— 12 ns clock to output
— 495 mW (Commercial)
— 660 mW (Military)
INIT
A
A
A
A
A
A
A
A
A
A
9
8
7
6
5
4
3
2
1
0
CP
E
E
S
DECODER
ADDRESS
ADDRESS
ADDRESS
COLUMN
CC
ROW
, commercial and military
PROGRAMMABLE
ARRAY
Commercial
Military
MUL TIPLEXER
3901 North First Street
7C235A-25
25
12
90
TRIGGERED
REGISTER
EDGE-
8-BIT
CP
Functional Description
The CY7C235A is a high-performance 1024-word by 8-bit
electrically programmable read only memory packaged in a
slim 300-mil plastic or hermetic DIP, 28-pin leadless chip
carrier, or 28-pin plastic leaded chip carrier. The memory cells
utilize proven EPROM floating gate technology and byte-wide
intelligent programming algorithms.
The CY7C235A replaces bipolar devices pin for pin and offers
the advantages of lower power, superior performance, and
high programming yield. The EPROM cell requires only 12.5V
for the supervoltage, and low current requirements allow for
gang programming. The EPROM cells allow for each memory
location to be tested 100%, as each location is written into,
erased, and repeatedly exercised prior to encapsulation. Each
PROM is also tested for AC performance to guarantee that the
product will meet AC specification limits after customer
programming.
• Capable of withstanding greater than 2001V static
discharge
7C235A-30
30
15
90
1K x 8 Registered PROM
San Jose
O
O
O
O
O
O
O
O
7
6
5
4
3
2
1
0
GND
NC
O
A
A
A
A
A
4
3
2
1
0
0
Pin Configuration
O
O
O
A
A
A
A
A
A
A
A
7
5
4
1
0
0
1
2
6
3
2
5
6
7
8
9
10
11
7C235A-40
1
2
3
4
5
6
7
8
9
10
11
12
LCC/PLCC
12
4
Top View
Top View
CA 95134
1314151617
3 2 1
DIP
120
40
20
90
Revised December 27, 2002
28
24
23
22
21
20
19
18
17
16
15
14
13
27
18
26
E
V
A
A
E
INIT
CP
O
O
O
O
O
25
24
23
22
21
20
19
S
CC
8
9
7
6
5
4
3
E
INIT
E
CP
NC
O
O
S
7
6
CY7C235A
408-943-2600
Unit
mA
mA
ns
ns

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5962-88636033X Summary of contents

Page 1

... Selection Guide Minimum Address Set-Up Time Maximum Clock to Output Maximum Operating Commercial Current Military Cypress Semiconductor Corporation Document #: 38-04002 Rev Registered PROM • Capable of withstanding greater than 2001V static discharge Functional Description The CY7C235A is a high-performance 1024-word by 8-bit electrically programmable read only memory packaged in a slim 300-mil plastic or hermetic DIP, 28-pin leadless chip carrier, or 28-pin plastic leaded chip carrier ...

Page 2

... For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement. 5. See Introduction to CMOS PROMs in this Data Book for general information on testing. 6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. ...

Page 3

... SCOPE (b) High -ZLoad 2.0V System timing is simplified in that the on-chip edge-triggered register allows the PROM clock to be derived directly from the system clock without introducing race conditions. The on-chip register timing requirements are similar to those of discrete registers available in the market. The CY7C235A has an asynchronous initialize input (INIT). ...

Page 4

... PWC PWC t t PWC PWC t t HZC COS t RI programming information, including a listing of software packages, please see the PROM Programming Information located at the end of this section. Programming algorithms can be obtained from any Cypress representative. CY7C235A 7C235A-30 7C235A-40 Min. Max. Min. Max ...

Page 5

Table 1. Mode Selection Read or Output Disable Mode Other Read Output Disable Output Disable Initialize Program Program Verify Program Inhibit Intelligent Program Program Initialize Byte Blank Check Note “don’t care” but not to exceed V ±5%. ...

Page 6

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.6 1.4 1.2 1 MAX 0.6 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) CLOCK TO OUTPUT TIME vs. TEMPERATURE 1.6 1.4 ...

Page 7

Ordering Information Speed (ns Ordering Code CY7C235A-25PC 30 15 CY7C235A-30JC 40 20 CY7C235A-40PC CY7C235A-40DMB CY7C235A-40LMB MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups ...

Page 8

Package Diagrams (continued) Document #: 38-04002 Rev. *B 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 CY7C235A 51-85001-*A 51-80051-** Page ...

Page 9

... Document #: 38-04002 Rev. *B © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 10

... Document History Page Document Title: CY7C235A Registered PROM Document Number: 38-04002 Issue REV. ECN NO. Date ** 113857 03/06/02 *A 118893 10/09/02 *B 122243 12/27/02 Document #: 38-04002 Rev. *B Orig. of Change DSG Change from Spec number: 38-00229 to 38-04002 GBI Update ordering information RBI Add power up requirements to maximum ratings information. ...

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