5962-8981503KA E2V, 5962-8981503KA Datasheet - Page 8

• Manufacturer Part Number: 5962-8981503KA
• Manufacturer: E2V

Specifications of 5962-8981503KA

• Lead Free Status / RoHS Status: Not Compliant

If the asynchronous enable (E
the enable to a logic HIGH, and may be returned to the active state by switching the enable to a logic
LOW.
If the synchronous enable (E
upon the next positive clock edge after the synchronous enable input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic LOW, the subsequent positive clock edge will return the
output to the active state. Following a positive clock edge, the address and synchronous enable inputs
are free to change since no change in the output will occur until the next low-to-high transition of the
clock. This unique feature allows the QP7C245A decoders and sense amplifiers to access the next
location while previously addressed data remains stable on the outputs.
System timing is simplified in that the on-chip edge triggered register allows the PROM clock to be
derived directly from the system clock without introducing race conditions. The on-chip register timing
requirements are similar to those of discrete registers available in the market.
power-up and time-out sequences and can facilitate implementation of other sophisticated functions
such as a built-in “jump start” address. When activated, the initialize control input causes the contents
of a user-programmed 2049th 8-bit word to be loaded into the on-chip register. Each bit is
programmable and the initialize function can be used to load
any desired combination of 1s and 0s into the register. In the
unprogrammed state, activating INIT will generate a register
CLEAR (all outputs LOW). If all the bits of the initialize word
are programmed, activating INIT performs a register PRESET
(all outputs HIGH).
Applying a LOW to the INIT
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E
Mode Selection
Read
Output Disable
Initialize
Program
Program Verify
Program Inhibit
Intelligent Program
Program Synchronous Enable
Program Initialization Byte
Blank Check Zeros
/10 –
The QP7C245A has an asynchronous initialize input (INIT
QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
Read or Output Disable
X = “Don’t Care”, but not to exceed VCC +5%
Other
bar
) LOW.
bar
bar
input causes an immediate load
bar
S) is being used, the outputs will go to the OFF or high-impedance state
) is being used, the outputs may be disabled at any time by switching
A
A
A
A
A
A
A
A
A
A
A
A
10
10
10
10
10
10
10
10
10
10
10
10
-A
-A
-A
-A
-A
-A
-A
-A
-A
-A
-A
-A
4
4
4
4
4
4
4
4
4
4
4
4
V
V
A
A
A
A
A
A
A
A
A
A
IHP
IHP
3
3
3
3
3
3
3
3
3
3
A
A
A
A
A
A
A
A
A
A
A
A
2
2
2
2
2
2
2
2
2
2
2
2
-A
-A
-A
-A
-A
-A
-A
-A
-A
-A
-A
-A
1
1
1
1
1
1
1
1
1
1
1
1
bar
Pin Function
). The initialize function is useful during
V
V
A
A
A
A
A
A
A
A
A
A
PP
PP
0
0
0
0
0
0
0
0
0
0
Programmer Address
Decimal
V
2046
2047
2048
2049
PGM
IL
0
1
V
V
V
V
V
V
V
.
.
CP
X
X
IHP
IHP
IHP
IHP
/ V
ILP
ILP
ILP
/10
IH
E
E
VFY
V
V
V
V
V
V
V
V
V
V
S BAR
BAR,
Hex
7FE
7FF
IHP
IHP
IHP
IHP
IHP
000
001
800
801
ILP
ILP
IH
IL
IL
.
.
INIT
V
V
V
V
V
V
V
V
V
V
V
Page 8 of 11
PP
PP
PP
PP
PP
PP
PP
PP
IH
IH
IL
Control Byte
RAM Data
QP7C245A
Contents
Init Byte
High Z
High Z
High Z
Data
Data
Data
Data
Zeros
O
O
O
D
D
D
D
Byte
Init
.
.
7
7
7
7
7
7
7
-O
-D
-O
-D
-O
-D
-D
0
0
0
0
0
0
0