W83627DHG-P Nuvoton Technology Corporation of America, W83627DHG-P Datasheet
W83627DHG-P
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W83627DHG-P Summary of contents
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... W83627DHG-P W83627DHG-PT NUVOTON LPC I/O Date: July 09, 2009 Version: 1.94 ...
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... LPC Interface ..............................................................................................................................32 2 8.2 interface ................................................................................................................................34 8.3 Analog Inputs ...................................................................................................................... 35 8.3.1 Voltages Over 2.048 V or Less Than 0 V ....................................................................................35 8.3.2 Voltage Detection........................................................................................................................36 8.3.3 Temperature Sensing..................................................................................................................36 8.4 SST Command Summary ................................................................................................... 38 8.4.1 Command Summary ...................................................................................................................38 8.4.2 Combination Sensor Data Format...............................................................................................39 W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -I- Version 1.94 ...
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... Value RAM ⎯ Index 20h ~ 3Fh (Bank 0) ........................................................................... 78 9.29 9.30 Configuration Register - Index 40h (Bank 0) ...................................................................... 79 9.31 Interrupt Status Register 1 - Index 41h (Bank 0) ................................................................ 80 9.32 Interrupt Status Register 2 - Index 42h (Bank 0) ................................................................ 80 9.33 SMI# Mask Register 1 - Index 43h (Bank 0)....................................................................... 81 W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -II- Version 1.94 ...
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... III+-1 input source & output FAN select Register - Index 75h (Bank 0) .. 102 9.77 SYSTIN SMI# Shut-down mode High Limit Temperature Register - Index 76h (Bank 0) 103 9.78 SYSTIN SMI# Shut-down mode Low Limit Temperature Register - Index 77h (Bank 0) . 103 W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -III- Version 1.94 ...
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... Reserved Register - Index 5Ch ~ 5Fh (Bank 4) ......................................................... 119 Value RAM 2 ⎯ Index 50h-59h (Bank 5) ................................................................... 119 9.118 9.119 SYSFANIN SPEED HIGH-BYTE VALUE (RPM) - Index 50h (Bank 6)...................... 119 W83627DHG-P/W83627DHG-PT III+ input source & output FAN select Register - Index 5Eh Publication Release Date: July 09, 2009 -IV- Version 1.94 ...
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... UART FIFO Control Register (UFR) (Write only).....................................................................156 12.2.6 Interrupt Status Register (ISR) (Read only) .............................................................................156 12.2.7 Interrupt Control Register (ICR) (Read/Write)..........................................................................157 12.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)........................................................158 12.2.9 User-defined Register (UDR) (Read/Write) .............................................................................158 W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -V- Version 1.94 ...
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... Waken up by Mouse events ....................................................................................................180 15.3 Resume Reset Logic......................................................................................................... 181 15.4 PWROK Generation.......................................................................................................... 181 15.4.1 The Relation among PWROK/PWROK2, ATXPGD and FTPRST#.........................................182 16. SERIALIZED IRQ.................................................................................................................... 185 16.1 Start Frame ....................................................................................................................... 185 16.2 IRQ/Data Frame................................................................................................................ 186 W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -VI- Version 1.94 ...
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... Parallel Port Mode Parameters...........................................................................................259 22.4.11 Parallel Port ........................................................................................................................260 22.4.12 KBC Timing Parameters .....................................................................................................267 22.4.13 GPIO Timing Parameters....................................................................................................270 22.5 LPC Timing ....................................................................................................................... 272 23. TOP MARKING SPECIFICATIONS........................................................................................ 273 24. ORDERING INFORMATION................................................................................................... 274 25. PACKAGE SPECIFICATION .................................................................................................. 275 26. REVISION HISTORY .............................................................................................................. 276 W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -VII- Version 1.94 ...
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... Figure 8-2 Serial Bus Write to Internal Address Register Followed by the Data Byte .................... 34 Figure 8-3 Serial Bus Read from Internal Address Register........................................................... 34 Figure 8-4 Analog Inputs and Application Circuit of the W83627DHG-P........................................ 35 Figure 8-5 Monitoring Temperature from Thermistor...................................................................... 37 Figure 8-6 Monitoring Temperature from Thermal Diode (Voltage Mode)...................................... 37 Figure 8-7 Monitoring Temperature from Thermal Diode (Current Mode) ...
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... Table 15-2 Definitions of Mouse Wake-Up Events ....................................................................... 180 Table 15-3 Timing and Voltage Parameters of RSMRST# ........................................................... 181 Table 15-4 ..................................................................................................................................... 182 Table 15-5 Bit Map of Logical Device A, CR[E6h], Bits[3:1] ......................................................... 182 Table 15-6 ..................................................................................................................................... 183 Table 16-1 SERIRQ Sampling Periods ......................................................................................... 186 W83627DHG-P/W83627DHG- Mode ................................................................ 50 TM Mode ............................................................. 51 TM Mode ...
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... MART AN The W83627DHG-P supports four -- 360K, 720K, 1.2M, 1.44M, or 2.88M -- disk drive types and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s, 1 Mb/s, and 2 Mb/s. The disk drive adapter supports the functions of floppy disk drive controller (compatible with the industry standard 82077/ 765), data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic ...
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... Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation Programmable baud rate generator allows division of clock source by any value from Maximum baud rate for clock source 24 MHz is 1.5 M bps. W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 - Version 1.94 ...
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... Issue SMI#, OVT# to activate system protection TM Nuvoton Hardware Doctor Eight VID inputs / outputs 2 Provide I C interface to read / write registers Serial Peripheral Interface Support bits SPI Flash Memory with clock MHz Support Mode 0 and Mode 3 W83627DHG-P/W83627DHG-PT F MART III and S F MART AN MART ...
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... Simple Serial Transport™ Interface SST temperature and voltage Combination Sensor command support Support SST 0.9 Specification PECI Interface Support PECI 1.0 and 1.1a Specifications Support 4 CPU addresses and 2 domains per CPU address Package 128-pin QFP Pb-free/RoHS W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -4- Version 1.94 ...
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... GPIO I/O pins Hardware Monitor HM channel and Vref Keyboard/Mouse KBC data and clock VID I/O pins VID Serial Peripheral Interface SPI Figure 3-1 W83627DHG-P Block Diagram W83627DHG-P/W83627DHG-PT LPC Interface FDC UARTA UARTB IR PRT ACPI PECI Interface W83627DHG-P Publication Release Date: July 09, 2009 ...
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... VID3 VID3 125 125 VID2 VID2 126 126 VID1 VID1 127 127 VID0 VID0 128 128 Figure 4-1 Pin Layout for W83627DHG-P W83627DHG-P/W83627DHG-PT 3VSB 3VSB 3VSB 3VSB VBAT VBAT 3VSB 3VSB VBAT VBAT W83627DHG-P W83627DHG-P 3VCC 3VCC Publication Release Date: July 09, 2009 ...
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... Open-drain output pin with 12-mA sink capability Open-drain output pin with 24-mA sink capability Bi-direction pin with source capability and sink capability I/O - Bi-direction pin with source capability and sink capability W83627DHG-P/W83627DHG-PT for details. Publication Release Date: July 09, 2009 -7- Version 1.94 ...
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... This input pin needs to WP connect a pulled-up 1-KΩ resistor to 5V for Floppy Drive compatibility. W83627DHG-P/W83627DHG-PT DESCRIPTION System clock input, either 24MHz or 48MHz. The actual frequency must be specified in the register. The default value is 48MHz. Generated PME event. ...
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... OD 12 This pin is for Extension FDD B; its function is the same as the MOB# pin of FDC. EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; its function is the same as the MOB# pin of FDC. W83627DHG-P/W83627DHG-PT DESCRIPTION DESCRIPTION Publication Release Date: July 09, 2009 -9- Version 1.94 ...
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... EXTENSION FDD MODE: DIR2 This pin is for Extension FDD B; its function is the same as the DIR# pin of FDC. EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; its function is the same as the DIR# pin of FDC. W83627DHG-P/W83627DHG-PT DESCRIPTION Publication Release Date: July 09, 2009 -10- Version 1.94 ...
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... EXTENSION FDD MODE: WP2# IN This pin is for Extension FDD B; its function is the same as the WP# ts pin of FDC. EXTENSION 2FDD MODE: This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC. W83627DHG-P/W83627DHG-PT DESCRIPTION Publication Release Date: July 09, 2009 -11- Version 1.94 ...
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... This pin is a tri-state output. 12 EXTENSION 2FDD MODE: This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC. 5.4 Serial Port & Infrared Port Interface SYMBOL PIN I/O W83627DHG-P/W83627DHG-PT DESCRIPTION DESCRIPTION Publication Release Date: July 09, 2009 -12- Version 1.94 ...
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... UART. GP66 I/OD General-purpose I/O port 6 bit 6. 12t Clear To Send. This is the modem-control input. The function of CTSA these pins can be tested by reading bit 4 of the handshake status t register. W83627DHG-P/W83627DHG-PT DESCRIPTION Publication Release Date: July 09, 2009 -13- Version 1.94 ...
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... Note: This pin changes to input state during internal PWROK GP42* I/O 12t from low to high, then goes back to the previous setting state. (Please see the AP Note 1 of W83627DHG-P) Serial Input. This pin is used to receive serial data through the SINB communication link. IN ...
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... To initiate the data transfer between the W83627DHG-P and a slave device, SCE# must go low. This synchronizes the slave device with the W83627DHG-P. Data can now be transferred between the W83627DHG-P and the slave device in one of two modes: the data is sampled either on the rising or the falling edge of the clock. ...
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... Transfer commands, address or data to serial flash. This pin is connected serial flash. CASE OPEN detection. An active-low input from an external device when the case is open. This signal can be latched if pin VBAT is connected to the battery, even if the W83627DHG-P is turned off. Pulling up a 2-MΩ resistor to VBAT is recommended if not in use. ...
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... SST Interface SYMBOL PIN I/O SST 114 I/O V4 W83627DHG-P/W83627DHG-PT DESCRIPTION amplitude fan tachometer input amplitude fan tachometer input. (Default) General-purpose I/O port 2 bit 1. DC/PWM fan output control. CPUFANOUT0 and AUXFANOUT are default PWM mode, CPUFANOUT1 and SYSFANOUT are default DC mode. DC/PWM fan output control. (Default) CPUFANOUT0 and AUXFANOUT are default PWM mode, CPUFANOUT1 and SYSFANOUT are default DC mode ...
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... ACPI supports the functions of thermal management, state management, and speed control, as well as the global system states and different device power states. Two of the primary states that the W83627DHG-P supports are the S0 (working) and S3 (suspend to RAM) states full-power state, in which the computer is actively used sleeping state, in which the processor is powered down, but the memory, where the last procedural state is stored, is still active ...
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... MDAT I/OD 16ts GP25 I/OD 16t 65 MCLK I/OD 16ts W83627DHG-P/W83627DHG-PT DESCRIPTION PCI Reset Buffer 2. (Default) General-purpose I/O port 3 bit 2. Serial Bus clock. PCI Reset Buffer 3. (Default) General-purpose I/O port 3 bit 3. Serial bus bi-directional Data. POWER SOURCE DESCRIPTION General-purpose I/O port 2 bit 0. ...
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... Connect to the reset button. This pin has internal de-bounce FTPRST circuit whose de-bounce time is at least 32 mS. GP37 I/OD General-purpose I/O port 3 bit 7. 12t 64 SUSC# IN SLP_S5# input. t W83627DHG-P/W83627DHG-PT DESCRIPTION General-purpose I/O port 2 bit 6. Keyboard Data. General-purpose I/O port 2 bit 7. Keyboard Clock. DESCRIPTION Publication Release Date: July 09, 2009 -20- Version 1.94 ...
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... Panel Switch Input. PSIN resistor. GP57 I/OD General-purpose I/O port 5 bit 7. 12t 67 Panel Switch Output. This signal is used to wake-up the system PSOUT from S3/S5 state. W83627DHG-P/W83627DHG-PT DESCRIPTION This pin is active-low with an internal pulled-up Publication Release Date: July 09, 2009 -21- Version 1.94 ...
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... I/OD FTPRST GP36 I/OD 5.14 POWER PINS SYMBOL PIN 3VSB 61 W83627DHG-P/W83627DHG-PT DESCRIPTION This GPxx* can serve as GPIO or the Watchdog Timer output signals. This GPxx*** can serve as GPIO or Suspend-LED output signals. DESCRIPTION SLP_S5# input. t General-purpose I/O port 3 bit 7 12t During VSB power reset (RSMRST#), this pin is pulled down internally and is defined as EN_ACPI (enabling particular ACPI functions), which provides the value for CR2C bit 4 (EN_ACPI) ...
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... Analog +3.3 V power input. Internally supply power to all analog AVCC 95 circuits. CPUD- Analog ground. The ground reference for all analog input. 105 Internally connected to all analog circuits. (AGND) VSS 20,55 Ground. Vtt 107 INTEL W83627DHG-P/W83627DHG-PT DESCRIPTION ® CPU Vtt power. Publication Release Date: July 09, 2009 -23- Version 1.94 ...
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... This pin generates the PWRGD signals while 3VCC is present. ATX power good input signal connected to the PWROK signal ATXPGD 87 from the power supply for PWROK/PWRGD generation. The default is enabled. t1 RSMRST# V1 3VSB FTPRST# PWROK 3VCC W83627DHG-P/W83627DHG-PT DESCRIPTION Publication Release Date: July 09, 2009 -24- V2 Version 1.94 ...
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... VSBGATE# 3VCC PSON# t6 SUSB# SUSC# S0 RSTOUTx# LRESET# 3VCC 3VCC Internal PWROK PWROK W83627DHG-P/W83627DHG- t10 V3 t2 Publication Release Date: July 09, 2009 -25- Version 1.94 ...
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... Valid Voltage 3VSB Ineffective Voltage V2 3VCC Valid Voltage V3 3VCC Ineffective Voltage V4 Note： 1. The values above are the worst-case results of R&D simulation. 2. The length of T level is based on the length of the low level of FTPRST# L W83627DHG-P/W83627DHG-PT PWROK_2 / PWROK V4 PARAMETER MIN TYPICAL MAX - - 3.0 2.4 ...
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... CONFIGURATION REGISTER ACCESS PROTOCOL The W83627DHG-P uses Super I/O protocol to access configuration registers to set up different types of configurations. The W83627DHG-P has totally twelve Logical Devices (from Logical Device 0 to Logical Device C with the exception of Logical Device 4 for backward compatibility) corresponding to twelve individual functions: FDC (Logical Device 0), Parallel Port (Logical Device 1), UARTA (Logical Device 2), UARTB (Logical Device 3), Keyboard Controller (Logical Device 5), SPI (Serial Peripheral Interface, Logical Device 6), GPIO6 (Logical Device 7), WDTO# & ...
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... Is the data “87h”? “87h”? Extended Function Extended Function Figure 7-3 Configuration Register To program the W83627DHG-P configuration registers, the following configuration procedures must be followed in sequence: (1). Enter the Extended Function Mode. (2). Configure the configuration registers. (3). Exit the Extended Function Mode. W83627DHG-P/W83627DHG-PT ...
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... DX, 2EH MOV AL, 87H OUT DX, AL OUT DX, AL ;----------------------------------------------------------------------------- ; Configure Logical Device 1, Configuration Register CRF0 ;----------------------------------------------------------------------------- MOV DX, 2EH MOV AL, 07H OUT DX point to Logical Device Number Reg. MOV DX, 2FH MOV AL, 01H OUT DX select Logical Device 1 ; MOV DX, 2EH W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -29- Version 1.94 ...
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... R/W 29h R/W 2Ah R/W 2Bh 2Ch R/W 2Dh R/W 2Eh R/W 2Fh R/W S: Strapping; x: chip version. W83627DHG-P/W83627DHG-PT DEFAULT VALUE 00h B0h 7xh FFh Device Power Down 00h Immediate Power Down 0100_0ss0b 00h Interface Tri-state Enable 0s000000b Reserved 50h 00h ...
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... The W83627DHG-P provides hardware access to all monitored parameters through the LPC or I interface and software access through application software, such as Nuvoton’s Hardware Doctor BIOS. In addition, the W83627DHG-P can generate pop-up warnings or beep tones when a parameter goes outside of a user-specified range. ...
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... Access Interfaces The W83627DHG-P provides two interfaces, LPC and I internal registers of the hardware monitor. 8.2.1 LPC Interface This interface uses the LPC bus to access the index and data ports. These two ports are located at the 16-bit port specified in CR60 and CR61, plus 5h and 6h, respectively. If the 16-bit port value is 290h, so the default index and data port addresses are 295h and 296h, respectively ...
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... Port 6h Port 6h Port 6h Data Data Data Data Register Register Register Register Figure 8-1 LPC Bus' Reads from / Writes to Internal Registers W83627DHG-P/W83627DHG-PT Smart Fan Configuration Smart Fan Configuration Smart Fan Configuration Smart Fan Configuration Registers Registers Registers Registers 00h-1Fh 00h-1Fh 00h-1Fh 00h-1Fh ...
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... I C interface 2 This interface uses the I C Serial Bus to access the internal registers. The W83627DHG-P has a programmable serial-bus address that is controlled by index 48h. The two timing diagrams below illustrate how to use the I and how to read the value in an internal register, respectively. ...
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... R THM 10K@25 C, beta=3435K Figure 8-4 Analog Inputs and Application Circuit of the W83627DHG-P As illustrated in the figure above, other connections may require some external circuits. The rest of this section provides more information about voltages outside the range of the 8-bit ADC, CPU Vcore voltage detection, and temperature sensing 8 ...
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... The W83627DHG-P uses the same approach. Pins 12 and 95 provide two functions. One, these pins are connected to VCC at +3 supply internal (digital / analog) power to the W83627DHG-P. Two, these pins monitor VCC. The W83627DHG-P has two internal, 34-KΩ serial resistors that reduce the ADC-input voltage to 1 ...
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... Monitor Temperature from Thermal Diode (Voltage Mode) The thermal diode D- pin is connected to CPUD- (pin 105), and the D+ pin is connected to the temperature sensor pin in the W83627DHG-P. A 15-KΩ resistor is connected to VREF to supply the bias current for the diode, and the 2200-pF, bypass capacitor is added to filter high-frequency noise. ...
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... Diode Figure 8-7 Monitoring Temperature from Thermal Diode (Current Mode) The pin of processor D- is connected to CPUD- (pin 105) and the pin D+ is connected to temperature sensor pin in the W83627DHG-P. A bypass capacitor C=2200pF should be added to filter the high frequency noise. 8.4 SST Command Summary The W83627DHG-P is equipped with a built-in voltage and temperature sensor which uses the Simple Serial Transport (SST) interface ...
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... Voltage Data Format The W83627DHG-P can return five (5) voltage values through the SST interface. The voltage data format is 16-bit two’s-complement binary. The relation between the 2-byte data and the monitored voltage is listed below: 1) CPUVCORE (pin 100) = Decimal[2-byte data by GetVoltVccp 1024 volts ...
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... PECI is one of the temperature sensing methods that the W83627DHG-P supports. The W83627DHG-P contains a PECI master and reads the CPU PECI temperature. The CPU is a PECI client. The PECI temperature values returning from the CPU are in “counts” which are approximately linear in relation to changes in temperature in degrees centigrade ...
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... When the PECI temperature is below -20, the duty cycle is fixed at Duty2 to maintain a minimum (and constant) RPM for the CPU fan. W83627DHG-P’s fan control circuit can only accept positive real-time temperature inputs and limits setting (in Smart Fan ™ mode). The device provides offset registers to ‘shift’ the negative PECI readings to positive values otherwise the fan control circuit will not function properly ...
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... The value of 55 (hex) will appear in the relevant real-time temperature register. While using Smart Fan control function of W83627DHG-P, BIOS/software must include Tbase in determining the thresholds (limits). In this example, assuming TControl is -10 and Tbase is set to 100 (1) , the threshold temperature value corresponding to the “ ...
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... PECI Host Figure 8-10 Block Diagram for PECI 1.0 The W83627DHG-P provides a PECISB pin that can be connected to a PECI host (e.g. chipset), so the W83627DHG-P becomes a bridge between that PECI host and the PECI client (e.g. CPU with PECI function). The bridge can pass the CPU PECI signals by programming Configure Register at Logical Device C, CR [E5h] Bit 0 ...
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... This section is divided into two parts, one to measure the speed and one to control the speed. 8.6.1 Fan Speed Measurement The W83627DHG-P can measure fan speed for fans equipped with tachometer outputs. The tachometer signals should be set to TTL-level, and the maximum input voltage cannot exceed +3 the tachometer signal exceeds +3 external trimming circuit should be added to reduce the voltage accordingly ...
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... Fan Speed Control The W83627DHG-P has four output pins for fan control, each of which offers PWM duty cycle and DC voltage to control the fan speed. The output type (PWM or DC) of each pin is configured by Bank0 Index 04h, bits Index 12h, bit 0; and Index 62h, bit 6. ...
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... TM 8.6 Control MART AN The W83627DHG-P supports two S MART TM TM Cruise mode III features, and S MART AN in the following sections. Each fan output and corresponding temperature sensor is illustrated in the figure below. SYSTIN S MART FANCTRL1 FANCTRL2 pre-configure FANOUT CPUTIN(Def.) 8'h00 PECI1 S MART PECI2 ...
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... S F MART AN PECI1 PECI2 PECI3 PECI4(Def.) FANCTRL5 TM FANCTRL5 S F III+ TEMP_SEL MART AN (Bank0, Idx75[3:1]) Figure 8-11 FANOUT and Corresponding Temperature Sensors in S W83627DHG-P/W83627DHG-PT (Bank6, Idx5C PECI ERROR FANCTRL5 S (Bank6, Idx5D III PECI ERROR FANCTRL5 S (Bank6, Idx5E) TM III+ PECI ERROR MART ...
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... The following figures illustrate two examples of Thermal Cruise W83627DHG-P/W83627DHG-PT TM mode: TM mode. Publication Release Date: July 09, 2009 -48- Version 1 ...
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... Tolerance Target Temperature 55°C Tolerance 52°C (V) DC 3.3 Output Voltage 1.65 0 Figure 8-13 Mechanism of Thermal Curise W83627DHG-P/W83627DHG- Fan Start = 20% Fan Stop = 10% Stop Time TM Mode (PWM Duty Cycle Fan Start = 0.62V Fan Stop = 0.31V Fan Start = 0.62V Stop Time TM Mode (DC Output Value) ...
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... Bank 0 Index Current SYS Temperature 27h Bank2 Index Current AUX Temperature 50h,51h Current Bank0 Index CPUFANOUT0 03h Output Value Current Bank0 Index SYSFANOUT 01h W83627DHG-P/W83627DHG-PT TM mode Mode TM mode Mode MART AN REGISTER NAME ATTRIBUTE CPUTIN Temperature Read only Sensor SYSTIN Temperature ...
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... SPEED TARGET-SPEED TM CRUISE COUNT MODE SYSFANOUT Bank0, Index 05h CPUFANOUT0 Bank0, Index 06h AUXFANOUT Bank0, Index 13h CPUFANOUT1 Bank0, Index 63h W83627DHG-P/W83627DHG-PT REGISTER NAME ATTRIBUTE AUXFANOUT Output FFh Value Select CPUFANOUT1 Output 80h / FFh by Value Select strapping TM Mode KEEP MIN. START- ...
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... The target temperature, temperature tolerance, maximum and minimum fan outputs and step are set. (2) The following figure shows the initial conditions. If the current temperature is within (Target Temperature ± Temperature Tolerance), the fan speed remains constant. W83627DHG-P/W83627DHG-PT Pin 115 CPUFANOUT0 Pin 120 ...
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... Min. Fan Output TM Figure 8- MART AN If the current temperature rises higher than (Target Temperature 1 + Temperature Tolerance), the fan speed will rise one step, and the target temperature will shift to (Target Temperature 1 + W83627DHG-P/W83627DHG-PT Setting Setting Setting Tolerance Tolerance Tolerance Tar. + Tol. Tar. + Tol. ...
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... The stop value is enabled by register Bank0 Index 12h, bit 4 and bit 6, and the stop value is specified in Bank0 Index 09h and Index 64h. The fan remains at the stop value for the period of time defined in Bank0 Index 0Dh and Index 66h. W83627DHG-P/W83627DHG-PT Tar Tar Tar 2 ...
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... Bank0, Index 06h CPUFANOUT1 Bank0, Index 63h III MART AN OUTPUT STEP MODE CPUFANOUT0 Bank0, Index 68h CPUFANOUT1 Bank0, Index 6Ah W83627DHG-P/W83627DHG- III Mode MART AN REGISTER NAME ATTRIBUTE CPUTIN Temperature Read only Sensor SYSTIN Temperature Read only Sensor AUXTIN Temperature Read only ...
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... DC/PWM3 are the fan output set. Assume Tx and Ty are the current temperature and DC/PWMx and DC/PWMy are the fan outputs, then The slope Fan Output PWMx DC / PWMy Fan output Fan output (DC/PWM) (DC/PWM) DC/PWM3 DC/PWM3 DC/PWMy DC/PWMy DC/PWM2 DC/PWM2 DC/PWMx DC/PWMx DC/PWM1 DC/PWM1 T1 T1 Figure 8-18 S W83627DHG-P/W83627DHG- − PWM PWM − − PWM PWM ...
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... DC/PWM 2 TM FANCTRL6 SMART FAN Bank1 Index III + 5Dh DC/PWM 3 TM FANCTRL6 SMART FAN Bank1 Index III + 5Eh, bit5-1 input source & output FAN select W83627DHG-P/W83627DHG- III+ Mode MART AN REGISTER NAME TM FANCTRL5 SMART FAN III + Temperature 1 TM FANCTRL5 SMART FAN III ...
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... The SMI# pin can create an interrupt if a fan count crosses a specified fan limit (rises above it or falls below it). This interrupt must be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. This mode is illustrated in the figure above. W83627DHG-P/W83627DHG-PT Fan Count limit SMI# ...
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... Temperature). This interrupt can be reset by reading all the interrupt status registers, or subsequent events do not generate interrupts. If the interrupt is reset, the SMI# pin continues to create interrupts until the temperature goes below T W83627DHG-P/W83627DHG-PT (Temperature Hysteresis) lower than T HYST . This interrupt must be reset by reading ...
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... In this mode, the SMI# pin can create an interrupt when the current temperature rises above T Once the temperature rises above T generate additional interrupts, even if the temperature remains above T falls below T . This interrupt must be reset by reading all the interrupt status registers, or HYST subsequent events do not generate interrupts. This is illustrated in the following figure. W83627DHG-P/W83627DHG- HYST SMI# * ...
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... Low Limit Temperature HTST HTST SMI# SMI Interrupt Reset when Interrupt Status Registers are read * Interrupt Reset when Interrupt Status Registers are read W83627DHG-P/W83627DHG- One-Time Interrupt Mode . This interrupt must be reset by reading HYST * * * * * * * * Shut-down Interrupt Mode Publication Release Date: July 09, 2009 ...
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... SYSTIN, CPUTIN, and AUXTIN by Bank0 Index 18h, bit 6; Bank0 Index 4Ch, bit 3; and Bank0 Index 4Ch, bit4. The OVT# pin has two interrupt modes, comparator and interrupt. The modes are illustrated in this figure. W83627DHG-P/W83627DHG- HYST ...
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... O even if the temperature remains above T be reset by reading all the interrupt status registers. The OVT# pin is asserted when an interrupt is generated and remains asserted until the interrupt is reset. W83627DHG-P/W83627DHG- and has not yet fallen below T O ...
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... Figure 8-24 Caseopen Mechanism 8.7.4 BEEP Alarm Function The W83627DHG-P provides an alarm output function at the BEEP/SO pin. The BEEP/SO pin is a multi-function pin and can be configured as BEEP output, if Configuration Register CR [24h], bit 1 is set to zero. The BEEP outputs a warning tone when one of the monitored parameters in the following events is out of the preset range ...
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... BEEP/ open-drain output pin and its default state is low. When the BEEP alarm function is activated, this pin repeatedly outputs 600 Hz square wave for 0.5 second and 1.2 KHz square wave for 0.5 second in turn until the enable bit or the abnormal event is cleared. W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -65- ...
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... NAME 0 0 DEFAULT BIT 7-0 Data to be read from written to Value RAM and Register. 9.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME PWM_CLK_SEL1 0 0 DEFAULT W83627DHG-P/W83627DHG- 00h (Address Pointer) DESCRIPTION Data DESCRIPTION 5 ...
Page 77
... Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT FUNCTION MODE PWM Output DESCRIPTION (Bank 0, Index 04h, bit DEFAULT DC Voltage Output (Bank 0, Index 04h, bit DESCRIPTION DEFAULT W83627DHG-P/W83627DHG-PT DESCRIPTION Input Clock 1 ∗ = Pre_Scale Divider 256 SYSFANOUT VALUE The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100% ...
Page 78
... Attribute: Read/Write Size: 8 bits 7 6 BIT NAME DEFAULT FUNCTION MODE PWM Output (Bank 0, Index DESCRIPTION 04h, bit DEFAULT DC Voltage Output (Bank 0, DESCRIPTION Index 04h, bit DEFAULT W83627DHG-P/W83627DHG- PWM_SCALE2 DESCRIPTION Input Clock 1 ∗ Pre_Scale Divider 256 CPUFANOUT0 VALUE Strap by FAN_SET (Pin 117) ...
Page 79
... SYSFANOUT pin produces DC output. (Default) 9.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h (Bank 0) Attribute: Read/Write Size: 8 bits FUNCTION MODE TM Thermal Cruise DESCRIPTION DEFAULT Fan Speed DESCRIPTION TM Cruise DEFAULT W83627DHG-P/W83627DHG- SYSFANOUT_MODE CPUFANOUT0_SEL DESCRIPTION TM Mode. TM Mode III Mode. MART ...
Page 80
... FUNCTION MODE TM Thermal Cruise DESCRIPTION MART AN III DEFAULT Fan Speed DESCRIPTION TM Cruise DEFAULT 9.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT W83627DHG-P/W83627DHG- Reserved CPUTIN Target Temperature CPUFANIN0 Target Speed Tolerance of CPUTIN Target ...
Page 81
... Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT TM In Thermal Cruise mode, CPUFANOUT0 value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan. W83627DHG-P/W83627DHG- CPUFANOUT0 STOP VALUE III mode, the CPUFANOUT0 value decreases to this eight SYSFANOUT START-UP VALUE ...
Page 82
... FANOUT to decrease its MART AN value by one step. (1)For PWM output: The units are intervals of 0.1 seconds. The default time is 1 seconds. (2)For DC output: The units are intervals of 0.4 seconds. The default time is 4 seconds. W83627DHG-P/W83627DHG- SYSFANOUT STOP TIME 1 1 ...
Page 83
... PWM output frequency. PWM output frequency = The maximum value of the divider is 127 (7Fh), and it should be set to 0. The register is only meaningful when AUXFANOUT is programmed for PWM output Bank0 Index 12h, bit 0 is 0). W83627DHG-P/W83627DHG- FANOUT VALUE STEP UP TIME ...
Page 84
... CPUFANOUT1 value decreases to zero when the temperature goes below the target range. 1: CPUFANOUT1 value decreases to the value specified in Index 64h when the temperature goes below the target range. 5 SYSFANOUT_MIN_VALUE. 0: SYSFANOUT value decreases to zero when the temperature goes below the target range. W83627DHG-P/W83627DHG- AUXFANOUT Value 1 1 ...
Page 85
... AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME AUXTIN Target Temperature / AUXFANIN0 Target Speed 0 0 DEFAULT FUNCTION MODE TM Thermal Cruise DESCRIPTION DEFAULT Fan Speed DESCRIPTION TM Cruise DEFAULT W83627DHG-P/W83627DHG-PT DESCRIPTION TM Mode. TM Mode Reserved AUXTIN Target Temperature ...
Page 86
... AUXFANOUT Start-up Value Register - Index 16h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT TM In Thermal Cruise mode, the AUXFANOUT value increases from zero to this eight-bit register value to provide a minimum value to turn on the fan. W83627DHG-P/W83627DHG- Reserved Tolerance of AUXTIN Target Temperature Reserved Tolerance ...
Page 87
... DEFAULT BIT 7 RESERVED. 6 DIS_OVT1. 0: Enable SYSTIN OVT# output. 1: Disable temperature sensor SYSTIN over-temperature (OVT#) output. (Default) 5 RESERVED. 4 OVT1_MODE. 0: Compare Mode. (Default) 1: Interrupt Mode. 3-0 RESERVED. 9.28 Reserved Registers - Index 19h ~ 1Fh (Bank 0) W83627DHG-P/W83627DHG- AUXFANOUT STOP TIME RESERVED OVT1_MODE DESCRIPTION Publication Release Date: July 09, 2009 ...
Page 88
... VIN3 Low Limit 39h SYSTIN temperature sensor High Limit 3Ah SYSTIN temperature sensor Hysteresis Limit SYSFANIN Fan Count Limit 3Bh Note the number of counts of the internal clock for the Limit of the fan speed. W83627DHG-P/W83627DHG-PT DESCRIPTION Publication Release Date: July 09, 2009 -78- Version 1.94 ...
Page 89
... SMI#Enable. A one enables the SMI# Interrupt output. Start. A one enables startup of monitoring operations. A zero puts the part in standby mode. 0 Note: Unlike the “INT_Clear” bit, the outputs of interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred. W83627DHG-P/W83627DHG-PT DESCRIPTION ...
Page 90
... AUXFANIN0. A one indicates the fan count limit of AUXFANIN0 has been exceeded. 2 VIN2. A one indicates the high or low limit of VIN2 has been exceeded. 1 VIN3. A one indicates the high or low limit of VIN3 has been exceeded. 0 VIN1. A one indicates the high or low limit of VIn1 has been exceeded. W83627DHG-P/W83627DHG- CPUTIN SYSTIN ...
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... TAR2 TAR1 AUXTIN 1 1 DEFAULT BIT 7 TAR2 6 TAR1 5 AUXTIN 4 CASEOPEN 3 AUXFANIN0 2 VIN2 1 VIN3 0 VIN1 W83627DHG-P/W83627DHG- CPUTIN SYSTIN 3VCC AVCC DESCRIPTION A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 1 – Index 41h (Bank0 CASEOPEN AUXFANIN0 ...
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... CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit will 7 not be self cleared. Please write 0 after the event is cleared. The function is the same as LDA, CR [E6h], bit 5. 6 Reserved. 5 Shut_AUX 4 Shut_CPU Shut_SYS 3 2 AUXFANIN1. 1 CPUFANIN1. 0 Reserved. W83627DHG-P/W83627DHG- Shut_AUX DESCRIPTION Shut_AUX Shut_CPU Shut_SYS ...
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... Read/Write Size: 8 bits 7 6 BIT RESERVED NAME 0 0 DEFAULT BIT 7 RESERVED. (Read only) 6-0 SERIAL BUS ADDR. Serial Bus address <7:1>. W83627DHG-P/W83627DHG- SYSFANIN SYSFANIN FANOPV4 FANINC4 DIV_B1 DIV_B0 DESCRIPTION CPUFANIN0 Divisor, bits 1-0. (See VBAT Monitor Control Register – Index 5Dh (Bank 0)) SYSFANIN Divisor, bits 1-0 ...
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... AUXFANOUT NAME TEMP_SEL[2] TEMP_SEL[ DEFAULT BIT 7 RESERVED. 6 AUXFANOUT TEMP_SEL[2]. 5 AUXFANOUT TEMP_SEL[1]. 4 AUXFANOUT TEMP_SEL[0]. 3 RESERVED. 2 CPUFANOUT0 TEMP_SEL[2]. W83627DHG-P/W83627DHG- AUXFANOUT RESERVED CPUFANOUT0 TEMP_SEL[0] TEMP_SEL[ DESCRIPTION AUXFANOUT Temperature Source Select. Bits Select AUXTIN as AUXFANOUT monitor source (Default). Please be noted that the temperature source / reading in the Bank 2, Index 50 and 51, AUXTIN Temperature Sensor is AUXTIN when this is selected ...
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... NAME TEMP_SEL[2] TEMP_SEL[ DEFAULT BIT 7 CPUFANOUT1 TEMP_SEL[2]. W83627DHG-P/W83627DHG-PT DESCRIPTION source (Default). Please be noted that the temperature source / reading in the Bank 1, Index 50 and 51, CPUTIN Temperature Sensor is CPUTIN when this is selected Reserved Select PECI Agent 1 as CPUFANOUT0 monitor source. Please be noted that the ...
Page 96
... RESERVED. These two bits should be set to 01h, the default value. 1-0 RESERVED. 9.42 SMI#/OVT# Control Register - Index 4Ch (Bank 0) Attribute: Read/Write Size: 8 bits W83627DHG-P/W83627DHG-PT DESCRIPTION Select CPUTIN as CPUFANOUT1 monitor source Select AUXTIN as CPUFANOUT1 monitor source Reserved Select PECI Agent 1 as CPUFANOUT1 monitor source ...
Page 97
... RESERVED NAME 1 0 DEFAULT BIT 7-6 RESERVED. 5 FANOPV3. AUXFANIN0 output value, only if bit 4 is set to zero. 1: Pin 111 (AUXFANIN0) generates a logic-high signal. 0: Pin 111 generates a logic-low signal. (Default) 4 FANINC3. AUXFANIN0 Input Control. W83627DHG-P/W83627DHG- EN_T1 DIS_ DIS_ OVTPOL _ONE OVT3 OVT2 DESCRIPTION ...
Page 98
... Enable BEEP output. 0: Disable BEEP output. (Default) 4 EN_CPUFANIN1_BP. BEEP output control for CPUFANIN1 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) 3 RESERVED. This bit should be set BANKSEL2. 1 BANKSEL1. 0 BANKSEL0. W83627DHG-P/W83627DHG-PT DESCRIPTION EN_CPUFANIN1 RESERVED BANKSEL2 _BP _BP DESCRIPTION Bank Select for Index Ports 0x50h ~ 0x5Fh ...
Page 99
... BIT NAME 0 1 DEFAULT 7 6 BIT NAME 1 0 DEFAULT BIT 15-8 Vendor ID High-Byte, if Index 4Eh, bit Default 5Ch. 7-0 Vendor ID Low-Byte, if Index 4Eh, bit Default A3h. 9.46 Reserved Register - Index 50h ~ 55h (Bank 0) W83627DHG-P/W83627DHG- VIDH VIDL DESCRIPTION Publication Release Date: July 09, 2009 ...
Page 100
... EN_VIN0_BP. BEEP output control for VIN0 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) 0 EN_CPUVCORE_BP. BEEP output control for CPUVCORE if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) W83627DHG-P/W83627DHG- EN_ EN_ EN_ EN_ ...
Page 101
... EN_VIN2_BP. BEEP output control for VIN2 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) 0 EN_VIN1_BP. BEEP output control for VIN1 if the monitored value exceeds the threshold value. 1: Enable BEEP output. 0: Disable BEEP output. (Default) W83627DHG-P/W83627DHG- EN_ EN_ EN_ EN_VIN3 CASEOPEN ...
Page 102
... AUXFANIN1 DIV_B2. AUXFANIN1 Divisor, bit 2. (See VBAT Monitor Control Register – Index 5Dh (Bank 0)) 6~4 3 AUXFANIN1 DIV_B1. 2 AUXFANIN1 DIV_B0. 1 CPUFANIN1 DIV_B1 0 CPUFANIN1 DIV_B0 9.51 Reserved Register - Index 5Ah ~ 5Ch (Bank 0) 9.52 VBAT Monitor Control Register - Index 5Dh (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT W83627DHG-P/W83627DHG- CHIPID DESCRIPTION AUXFANIN1 AUXFANIN1 DIV_B1 DIV_B0 ...
Page 103
... Enable battery voltage monitor. When this bit changes from zero to one, it takes one monitor cycle time to update the VBAT reading value register. 0: disable battery voltage monitor. Fan divisor table: BIT 2 BIT 1 BIT 0 FAN DIVISOR W83627DHG-P/W83627DHG-PT SYSFANIN RESERVED DIODES3 DIODES2 DIV_B2 DESCRIPTION BIT 2 BIT 1 BIT ...
Page 104
... EN_SYSTIN CURRENT MODE. (To enable the current mode, please also set Bank0, Index 5Dh, Bit 1 to ‘1’) 1: Temperature sensing of SYSTIN by Current Mode. 0: Temperature sensing of SYSTIN depends on the setting of Index 5Dh. (Default) 0 RESERVED. 9.54 Reserved Register - Index 5Fh (Bank 0) W83627DHG-P/W83627DHG- EN_ EN_ EN_ ...
Page 105
... Attribute: Read/Write Size: 8 bits 7 6 BIT NAME DEFAULT FUNCTION MODE PWM Output DESCRIPTION (Bank 0, Index 62h, bit DEFAULT DC Output (Bank 0, Index 62h, bit 6 DESCRIPTION is 1) DEFAULT W83627DHG-P/W83627DHG- PWM_SCALE4 DESCRIPTION Input Clock 1 ∗ Pre_Scale Divider 256 CPUFANOUT1 Value Strap by FAN_SET2 (Pin 83) ...
Page 106
... BIT NAME 0 0 DEFAULT FUNCTION MODE TM Thermal Cruise DESCRIPTION MART AN DEFAULT III mode Fan Speed DESCRIPTION TM Cruise DEFAULT W83627DHG-P/W83627DHG- CPUFANOUT1_MODE TARGET TEMPERATURE TOLERANCE / CPUFANIN1 TARGET SPEED TOLERANCE DESCRIPTION TM Mode. TM Mode III Mode. MART AN In Fan Speed Cruise MART Tolerance of CPUFANIN1 Target Speed. ...
Page 107
... CPUFANOUT1 value to fall from the stop value to zero. (1)For PWM output: The units are intervals of 0.1 second. The default time is 6 seconds. (2)For DC output: The units are intervals of 0.4 second. The default time is 24 seconds. W83627DHG-P/W83627DHG- ...
Page 108
... CPUFANOUT1 Stop value. 9.65 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT III mode, the CPUFANOUT1 value decreases or increases by this eight-bit value, MART AN when needed. W83627DHG-P/W83627DHG- CPUFANOUT0 MAX. VALUE CPUFANOUT0 STEP ...
Page 109
... Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT TM In Thermal Cruise mode, when the function of AUXFANOUT temperature sensing is enabled, and the monitored temperature exceeds the threshold temperature, the AUXFANOUT will work at full speed. W83627DHG-P/W83627DHG- SYSFANOUT THRESHOLD TEMPERATURE CPUFANOUT0 CRITICAL TEMPERATURE 1 ...
Page 110
... AN TM 9.71 FANCTRL5 S F MART AN 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT TM 7 III+ Temperature 2 Register (T2). MART AN W83627DHG-P/W83627DHG- CPUFANOUT1 CRITICAL TEMPERATURE III+ Temperature 1 Register (T1) – Index 6Fh (Bank III+ Temperature 1 MART DESCRIPTION III+ Temperature 2 Register (T2) – Index 70h (Bank ...
Page 111
... MART AN TM 9.74 FANCTRL5 S F MART AN Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT TM 7 III+ DC/PWM 2 Register. MART AN W83627DHG-P/W83627DHG-PT III+ Temperature 3 Register (T3) – Index 71h (Bank III+-1 Temperature 3 MART DESCRIPTION III+ DC/PWM 1 Register - Index 72h (Bank III+ DC/PWM 1 ...
Page 112
... III+ MART III+ MART III+ MART SMART FAN III+-1 TEMP_SEL . Bits SYS Temperature CPU Temperature 3 AUX Temperature PECI1 PECI2 PECI3 PECI4 W83627DHG-P/W83627DHG-PT III+ DC/PWM 3 Register - Index 74h (Bank III+ DC/PWM 3 MART DESCRIPTION SMART FAN III+-1 SMART FAN FAN_SEL DESCRIPTION CPUFANOUT1 AUXFANOUT ...
Page 113
... SYSTIN SMI# Shut-down mode Low Limit Temperature. 9.79 CPUTIN SMI# Shut-down mode High Limit Temperature Register - Index 78h (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME CPUTIN SMI# Shut-down mode High Limit Temperature 0 0 DEFAULT BIT 7-0 CPUTIN SMI# Shut-down mode High Limit Temperature. W83627DHG-P/W83627DHG-PT DESCRIPTION DESCRIPTION ...
Page 114
... AUXTIN SMI# Shut-down mode High Limit Temperature. 9.82 AUXTIN SMI# Shut-down mode Low Limit Temperature Register - Index 7Bh (Bank 0) Attribute: Read/Write Size: 8 bits 7 6 BIT AUXTIN SMI# Shut-down mode Low Limit Temperature NAME 0 0 DEFAULT BIT 7-0 AUXTIN SMI# Shut-down mode Low Limit Temperature. W83627DHG-P/W83627DHG- DESCRIPTION ...
Page 115
... PECI2 PECI3 PECI4 9.84 Temperature Register - Index 7Dh (Bank 0) Attribute: Read Only Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-0 Temperature Register. (see Temperature selection Register – Index 7C (Bank 0)) W83627DHG-P/W83627DHG- MNTEMP2_SEL MNTEMP1_SEL DESCRIPTION Temperature Register DESCRIPTION Publication Release Date: July 09, 2009 ...
Page 116
... RESERVED 0 0 DEFAULT BIT 7-5 RESERVED. These bits should be set to zero. 4-3 FAULT. Number of faults to detect before setting OVT# output. This avoids false strapping due to noise. 2 RESERVED. This bit should be set to zero. 1 OVTMOD. OVT# Mode Select. W83627DHG-P/W83627DHG- TEMP<8:1> DESCRIPTION RESERVED DESCRIPTION 5 ...
Page 117
... C. 9.89 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME THYST<0> DEFAULT BIT 7 THYST<0>. Hysteresis temperature bit 0. The nine-bit value is in units of 0.5 6-0 RESERVED. W83627DHG-P/W83627DHG-PT DESCRIPTION THYST<8:1> DESCRIPTION RESERVED ...
Page 118
... TOVF<0>. Over-temperature bit 0. The nine-bit value is in units of 0.5 6-0 RESERVED. TM 9.92 FANCTRL6 S F MART AN 1) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT TM 7 III+ Temperature 1 Register (T1). MART AN W83627DHG-P/W83627DHG- TOVF<8:1> DESCRIPTION RESERVED DESCRIPTION III+ Temperature 1 Register (T1) – Index 58h (Bank ...
Page 119
... MART AN TM 9.95 FANCTRL6 S F MART AN Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7 III+ DC/PWM 1 Register. MART AN W83627DHG-P/W83627DHG-PT III+ Temperature 2 Register (T2) – Index 59h (Bank III+ Temperature 2 MART DESCRIPTION III+ Temperature 3 Register (T3) – Index 5Ah (Bank III+ Temperature 3 ...
Page 120
... III+ FAN_SEL. Bits SYSFANOUT MART III MART III+ MART III MART AN TM W83627DHG-P/W83627DHG-PT III+ DC/PWM 2 Register - Index 5Ch (Bank III+ DC/PWM 2 MART DESCRIPTION III+ DC/PWM 3 Register - Index 5Dh (Bank III+ DC/PWM 3 MART DESCRIPTION III+ input source & output FAN select Register - ...
Page 121
... AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2) Attribute: Read Only Size: 8 bits 7 6 BIT NAME TEMP<0> DEFAULT BIT 7 TEMP<0>. Temperature <0> of the AUXTIN sensor. The nine-bit value is in units of W83627DHG-P/W83627DHG-PT DESCRIPTION CPUFANOUT0 SYSFANOUT CPUFANOUT0 TEMP<8:1> DESCRIPTION RESERVED DESCRIPTION ...
Page 122
... AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 1 DEFAULT BIT 7-0 THYST<8:1>. Hysteresis temperature, bits 8-1. The nine-bit value is in units of 0.5 ° and the default W83627DHG-P/W83627DHG-PT DESCRIPTION FAULT RESERVED DESCRIPTION THYST<8:1> 0 ...
Page 123
... TOVF<8:1>. Over-temperature, bits 8-1. The nine-bit value is in units of 0.5 ° default 9.105 AUXTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 2) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME TOVF<0> DEFAULT BIT 7 TOVF<0>. Over-temperature, bit 0. The nine-bit value is in units of 0.5 6-0 RESERVED. W83627DHG-P/W83627DHG- RESERVED DESCRIPTION TOVF<8:1> DESCRIPTION ...
Page 124
... DEFAULT BIT 7-5 RESERVED. 4 TAR3. A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt Status Register 3 – Index 50h (Bank 4)). 3-2 RESERVED. 1 VBAT. 0 3VSB. 9.108 Reserved Register - Index 52h (Bank 4) W83627DHG-P/W83627DHG- CPUFANIN1 RESERVED TAR3 DESCRIPTION TAR3 RESERVED ...
Page 125
... Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-0 OFFSET<7:0> SYSTIN Temperature Offset Value. The value in this register is added to the monitored value so that the read value will be the sum of the monitored value and this offset value. W83627DHG-P/W83627DHG- EN_ RESERVED USER_BP DESCRIPTION OFFSET< ...
Page 126
... Reserved Register - Index 57h-58h (Bank 4) 9.114 Real Time Hardware Status Register I - Index 59h (Bank 4) Attribute: Read Only Size: 8 bits 7 6 BIT CPUFANIN0 SYSFANIN NAME _STS _STS 0 0 DEFAULT BIT 7 CPUFANIN0_STS. CPUFANIN0 Status. 1: The fan speed count is over the threshold value. W83627DHG-P/W83627DHG- OFFSET<7:0> DESCRIPTION OFFSET<7:0> DESCRIPTION 5 ...
Page 127
... The SYSTIN temperature has been over the target temperature for three minutes at full fan speed in the Thermal Cruise 0: The SYSTIN temperature has not reached the warning range. 5 AUXTIN_STS. AUXTIN Temperature Sensor Status. 1: The temperature exceeds the over-temperature value. 0: The temperature is under the hysteresis value. W83627DHG-P/W83627DHG-PT DESCRIPTION CASEOPEN AUXFANIN0 ...
Page 128
... RESERVED. 2 TAR3_STS. Smart Fan of AUXFANIN Warning Status. 1: The selected temperature has been over the target temperature for three minutes at full fan speed in Thermal Cruise 0: The selected temperature has not reached the warning range. 1 VBAT_STS. VBAT Voltage Status. W83627DHG-P/W83627DHG-PT DESCRIPTION TM mode VIN2 ...
Page 129
... Note the number of counts of the internal clock for the Low Limit of the fan speed. 9.119 SYSFANIN SPEED HIGH-BYTE VALUE (RPM) - Index 50h (Bank 6) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT W83627DHG-P/W83627DHG-PT DESCRIPTION DESCRIPTION SYSFANIN SPEED HIGH-BYTE VALUE DESCRIPTION Publication Release Date: July 09, 2009 -119- 1 ...
Page 130
... BIT 7-0 CPUFANIN0 SPEED HIGH-BYTE VALUE. 9.122 CPUFANIN0 SPEED LOW-BYTE VALUE (RPM) - Index 53h (Bank 6) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-0 CPUFANIN0 SPEED LOW-BYTE VALUE. W83627DHG-P/W83627DHG-PT DESCRIPTION SYSFANIN SPEED LOW-BYTE VALUE DESCRIPTION CPUFANIN0 SPEED HIGH-BYTE VALUE 0 0 ...
Page 131
... DEFAULT BIT 7-0 AUXFANIN0 SPEED LOW-BYTE VALUE. 9.125 CPUFANIN1 SPEED HIGH-BYTE VALUE (RPM) - Index 56h (Bank 6) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-0 CPUFANIN1 SPEED HIGH-BYTE VALUE. W83627DHG-P/W83627DHG- AUXFANIN0 SPEED HIGH-BYTE VALUE DESCRIPTION AUXFANIN0 SPEED LOW-BYTE VALUE ...
Page 132
... DEFAULT BIT 7-0 AUXFANIN1 SPEED HIGH-BYTE VALUE. 9.128 AUXFANIN1 SPEED LOW-BYTE VALUE (RPM) - Index 59h (Bank 6) Attribute: Read/Write Size: 8 bits 7 6 BIT NAME 0 0 DEFAULT BIT 7-0 AUXFANIN1 SPEED LOW-BYTE VALUE. W83627DHG-P/W83627DHG- CPUFANIN1 SPEED LOW-BYTE VALUE DESCRIPTION AUXFANIN1 SPEED HIGH-BYTE VALUE ...
Page 133
... Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT FUNCTION MODE DESCRIPTION PWM Output DEFAULT DESCRIPTION DC Output DEFAULT 9.131 FANCTRL3 pre-configured fan output value for PECI error - Index 5Ch (Bank 6) Attribute: Read/Write W83627DHG-P/W83627DHG- Reserved DESCRIPTION FANCTRL2 pre-configured fan output value FANCTRL2 PWM Duty Cycle. The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100% ...
Page 134
... BIT NAME 1 1 DEFAULT FUNCTION MODE DESCRIPTION PWM Output DEFAULT DESCRIPTION DC Output DEFAULT 9.133 FANCTRL5 pre-configured fan output value for PECI error - Index 5Eh (Bank 6) W83627DHG-P/W83627DHG- FANCTRL3 pre-configured fan output value FANCTRL3 PWM Duty Cycle. The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0% ...
Page 135
... Read/Write Size: 8 bits 7 6 BIT NAME 1 1 DEFAULT FUNCTION MODE DESCRIPTION PWM Output DEFAULT DESCRIPTION DC Output DEFAULT W83627DHG-P/W83627DHG- FANCTRL5 pre-configured fan output value FANCTRL5 PWM Duty Cycle. The PWM duty cycle is equal to this 8-bit value, divided by 255, times 100%. FFh creates a duty cycle of 100%, and 00h creates a duty cycle of 0% ...
Page 136
... The data are placed to the LPC bus by the Super I/O (W83627DHG-P) and returned to the South Bridge. All of the data are read in this manner. By setting the registers shown at Table 10.3, the Super I/O (W83627DHG-P) supports all the instructions given, such as erase, read, program, to SPI flash ...
Page 137
... CMD_Da(1) 3 CMD_Da(2) 4 CMD_Add(3) 5 CMD_Ad(3)_Da(1)_W 6 CMD_Ad(3)_Da(4)_W 7 CMD_Ad(4)_Da(4)_R 8 CMD_Ad(3)_Da(1)_R 9 CMD_Ad(3)_Da(2)_R W83627DHG-P/W83627DHG-PT Description ADD2 Address [19:16] ADD1 Address [15:8] ADD0 Address [7:0] Data byte 0 Data byte 1 Data byte 2 Data byte 3 Table 10-3 MODE FUNCTION Command only Command with 1byte data write Command with 2bytes data read ...
Page 138
... First, write the “Byte Program” instruction to Base+0. Then write the addresses into Base+2 ~ Base+3 and parameters to Base+4. Last, write 5X to Base+1. For correct programming, make sure the state of the device is ready and write enabled. * For more details, please see the Programming Guide of the W83627DHG-P. W83627DHG-P/W83627DHG-PT FUNCTION ...
Page 139
... FLOPPY DISK CONTROLLER 11.1 FDC Functional Description The floppy disk controller (FDC) of the W83627DHG-P integrates all of the logic required for floppy disk control. The FDC implements a FIFO which provides better system performance in multi-master systems, and the digital data separator supports data rates bits/sec. ...
Page 140
... Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk. W83627DHG-P/W83627DHG-PT Publication Release Date: July 09, 2009 -130- Version 1.94 ...
Page 141
... FDC Core The W83627DHG-P FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. ...
Page 142
... N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627DHG-P/W83627DHG- Command codes 0 0 HDS DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after ...
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... W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627DHG-P/W83627DHG- HDS DS1 DS0 Publication Release Date: July 09, 2009 -133- REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after ...
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... W 0 MFM Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627DHG-P/W83627DHG- Command codes 0 0 HDS DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after ...
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... C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (6) Version PHASE R Command Result W83627DHG-P/W83627DHG- HDS DS1 DS0 Publication Release Date: July 09, 2009 -135- REMARKS Command codes Sector ID information prior to command execution No data transfer takes ...
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... D7 D6 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627DHG-P/W83627DHG- HDS DS1 DS0 HDS DS1 DS0 Publication Release Date: July 09, 2009 -136- REMARKS Command codes Sector ID information prior to Command execution ...
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... Undefined ------------------- (10) Recalibrate PHASE R Command Execution (11) Sense Interrupt Status PHASE R Command Result R ---------------- ST0 ------------------------- R ---------------- PCN ------------------------- (12) Specify PHASE R Command ---------SRT ----------- | --------- HUT ---------- | W |------------ HLT ----------------------------------| ND W83627DHG-P/W83627DHG- HDS DS1 DS0 Command codes DS1 DS0 Head retracted to Track 0 Interrupt Command code Status information at the end of each seek operation ...
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... Result R ----------------------- PCN-Drive 0-------------------- R ----------------------- PCN-Drive 1 ------------------- R ----------------------- PCN-Drive 2-------------------- R ----------------------- PCN-Drive 3 ------------------- R --------SRT ------------------ | --------- HUT -------- R ----------- HLT -----------------------------------| ND R ------------------------ SC/EOT ---------------------- R LOCK EIS EFIFO POLL | ------ FIFOTHR -------- R -----------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE R Command W83627DHG-P/W83627DHG- Command codes 0 0 HDS DS1 DS0 Head positioned over proper cylinder on the diskette Configure information Internal registers written ...
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... Lock PHASE R Command W LOCK 0 0 Result (19) Sense Drive Status PHASE R Command Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- W83627DHG-P/W83627DHG- LOCK HDS DS1 DS0 Publication Release Date: July 09, 2009 -139- REMARKS Command Code REMARKS Command Code Status information about ...
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... Register Descriptions There are several status, data, and control registers in the W83627DHG-P. These registers are defined below, and the rest of this section provides more details about each one of them. ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 ...
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... WDATA TOGGLE. This bit changes state on every rising edge of the WD# output pin. 3 RDATA TOGGLE. This bit changes state on every rising edge of the RDATA# output pin. 2 WE. This bit indicates the complement of the WE# output pin. 1 RESERVED. 0 MOT EN A. This bit indicates the complement of the MOA# output pin. W83627DHG-P/W83627DHG- STEP F/F TRAK0# HEAD# INDEX NA ...
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... MOTOR ENABLE A. Motor A on when active high. 3 DMA & INT ENABLE. An active high signal enables DRQ/IRQ. 2 FDC RESET. Floppy Disk Controller Reset. An active low signal resets the FDC. 1-0 DRIVE SELECT. Bits Select Drive Reserved Reserved Reserved. W83627DHG-P/W83627DHG- DSA# WD F/F RDATA WE F/F F ...
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... DEFAULT BIT 7 MEDIA ID1. 6 MEDIA ID0. 5 DRIVE TYPE ID1. 4 DRIVE TYPE ID0. 3 FLOPPY BOOT DRIVE 1. 2 FLOPPY BOOT DRIVE 0. 1 TAPE SEL 1. 0 TAPE SEL 0. TAPE SEL W83627DHG-P/W83627DHG- RESERVED DESCRIPTION DRIVE DRIVE FLOPPY FLOPPY TYPE ID1 TYPE ID0 BOOT BOOT DRIVE 1 ...
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... POWER RESERVED NAME RESET DOWN 0 0 DEFAULT BIT 7 S/W RESET. This bit is the software reset bit. 6 POWER DOWN. 0: The FDC is in the normal mode. 1: The FDC is in the power-down mode. 5 RESERVED. 4 PRECOMP 2. W83627DHG-P/W83627DHG-PT TAPE SEL 0 DRIVE SELECTED NON-DMA CB RESERVED MODE DESCRIPTION ...
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... DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S W83627DHG-P/W83627DHG-PT DESCRIPTION precompensation. The following tables show the precompensation values for every combination of these bits. These two bits select the data rate of the FDC and reduced write-current control. Bits ...
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... The FIFO register stores data, commands, and parameters, and it provides disk- drive status information. In addition, data bytes pass through the data register to program or obtain results after a command. In the W83627DHG-P, this register is disabled after reset. The FIFO can enable it and change its values through the configure command. ...
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... If the FDC detects a CRC error in the data field error. 4 WC. Wrong Cylinder. 1 indicates wrong cylinder. 3 SH. Scan Equal Hit. 1: During execution of the Scan command, if the equal condition is satisfied error. 2 SN. Scan Not Satisfied. 1: During execution of the Scan command error. 1 BC. Bad Cylinder. 1: Bad Cylinder. W83627DHG-P/W83627DHG- RESERVED ND DESCRIPTION ...
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... DSKCHG# while the other bits remain in tri-state. The bit definitions are as follows BIT NAME DSKCHG 0 NA DEFAULT BIT 7 DSKCHG. 6-0 RESERVED. Reserved for the hard disk controller. During a read of this register, these bits are in tri-state. W83627DHG-P/W83627DHG-PT DESCRIPTION DESCRIPTION RESERVED NA NA ...
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... DSKCHG#. This bit indicates the status of the DSKCHG# input. 6-4 RESERVED. These bits are always a logic 0 during a read. 3 DMAEN. This bit indicates the value of DO register, bit 3. 2 NOPREC. This bit indicates the value of the NOPREC bit in the CC REGISTER. 1 DRATE1. 0 DRATE0. W83627DHG-P/W83627DHG- RESERVED DRATE1 ...
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... RESERVED NA NA DEFAULT BIT 7-3 RESERVED. These bits should be set NOPREC. This bit disables the precompensation function. It can be set by the software. 1 DRATE1. 0 DRATE0. W83627DHG-P/W83627DHG- RESERVED DESCRIPTION These two bits select data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates ...
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... If MSBE is set to logical 0, one stop bit is sent and checked. (2) If MSBE is set to logical 1 and the data length is 5 bits, one-and-a-half stop bits are sent and checked. (3) If MSBE is set to logical 1 and the data length bits, two stop bits are sent W83627DHG-P/W83627DHG- ...
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... DLS0. Data Length Select Bit 0. DLS1 The following table identifies the remaining UART registers. Each one is described separately in the following sections. W83627DHG-P/W83627DHG-PT DESCRIPTION These two bits define the number of data bits that are sent or checked in each serial character. DLS0 DATA LENGTH 0 ...
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... Baudrate BHL Bit 8 Divisor Latch BDLAB = 1 High *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. W83627DHG-P/W83627DHG-PT Table 12-1 Register Summary for UART Bit Number Data RX Data ...
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... CPU in the RBR or FIFO. When no data are left in the RBR or FIFO, the bit is set to logical 0. 12.2.3 Handshake Control Register (HCR) (Read/Write) This register controls pins used with handshaking peripherals such as modems and also controls the diagnostic mode of the UART BIT RESERVED NAME 0 0 DEFAULT W83627DHG-P/W83627DHG- TBRE SBD NSER PBER ...
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... TDSR. DSR# Toggling. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU. 0 TCTS. CTS# Toggling. This bit indicates that the CTS# pin has changed state after HSR was read by the CPU. W83627DHG-P/W83627DHG-PT DESCRIPTION DSR ...
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... This register reflects the UART interrupt status BIT NAME FIFOS ENABLED DEFAULT BIT 7-6 FIFOS ENABLED. These two bits are set to logical 1 when UFR, bit 5-4 RESERVED. These two bits are always logical 0. W83627DHG-P/W83627DHG- RESREVED DMA TRANSMITTER MODE FIFO RESET SELECT DESCRIPTION These two bits are used to set the active level of the receiver FIFO interrupt ...
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... EUSRI. Set this bit to logical 1 to enable the UART status register interrupt. 1 ETBREI. Set this bit to logical 1 to enable the TBR empty interrupt. 0 ERDRI. Set this bit to logical 1 to enable the RBR data ready interrupt. W83627DHG-P/W83627DHG-PT DESCRIPTION These two bits identify the priority level of the pending interrupt, as shown in the table below. ...
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... Unless specified, the error percentage for all of the baud rates is 0.16%. Note: Pre-Divisor is determined by CRF0 of UART A and B. 12.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. W83627DHG-P/W83627DHG-PT 16 –1). The output frequency of DECIMAL DIVISOR ERROR PERCENTAGE ...
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... PARALLEL PORT 13.1 Printer Interface Logic The W83627DHG-P parallel port can be attached to devices that accept eight bits of parallel data at standard TTL level. The W83627DHG-P supports the IBM XT/AT compatible parallel port (SPP), the bi-directional parallel port (BPP), the Enhanced Parallel Port (EPP), and the Extended Capabilities Parallel Port (ECP) on the parallel port ...
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... HOST CONNECTOR PIN NUMBER OF W83627DHG-P 17 13.2 Enhanced Parallel Port (EPP) The following table lists the registers used in the EPP mode and identifies the bit map of the parallel port and EPP registers. Some of the registers are used in other modes as well. Table 13-2 EPP Register Addresses ...
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... INIT#. A logical 0 starts the printer (50 microsecond pulse, minimum). 1 AUTO FD. A logical 1 causes the printer to line-feed after a line is printed. 0 STROBE. A logical 1 generates an active-high pulse for a minimum of 0.5 μs to clock data into the printer. Valid data must be present for a minimum of 0.5 μs before and after the strobe pulse. W83627DHG-P/W83627DHG- SLCT ...
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... This signal is active low. It denotes a data read or write operation. Nerror I Error; same as SPP mode. Ninits O This signal is active low. When it is active, the EPP device is reset to its initial operating mode. NAStrb O This signal is active low. It denotes an address read or write operation. 13.2.7 EPP Operation W83627DHG-P/W83627DHG- PD5 PD4 PD3 PD2 ...
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... Extended Capabilities Parallel (ECP) Port This port is software- and hardware-compatible with existing parallel ports, so the W83627DHG-P parallel port may be used in standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host-to-peripheral) and reverse (peripheral-to-host) directions ...
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... Ecr MODE Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. Each register (or pair of registers, in some cases) is discussed below. W83627DHG-P/W83627DHG-PT DESCRIPTION ECP Parallel Port mode Reserved Test mode Configuration mode I/O ECP MODES R/W ...
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... This bit reflects the nFault input. 2-0 RESERVED. These three bits are not implemented and are always logical 1 during a read. 13.3.4 Device Control Register (DCR) The bit definitions are as follows BIT RESERVED DIRECTOR NAME 1 1 DEFAULT W83627DHG-P/W83627DHG- PD5 PD4 PD3 PD2 ADDRESS OR RLE ...
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... CNFGA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10h is returned indicating an 8-bit implementation. 13.3.9 CNFGB (Configuration Register B) Mode = 111 The bit definitions are as follows BIT COMPRESS INTROVALUE NAME 0 0 DEFAULT W83627DHG-P/W83627DHG-PT DESCRIPTION IRQX2 IRQX1 IRQX0 ...
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... ECP parallel port and packed into bytes in the ecpDFifo EPP Mode. The EPP mode is activated if the EPP mode is selected Reserved. W83627DHG-P/W83627DHG-PT DESCRIPTION IRQ Resource Reflects other IRQ resources selected by PnP register (Default) ...
Page 178
... PError (nAckReverse) This signal is used to acknowledge a change in the direction of the transfer (asserted = forward). The peripheral drives this signal low I to nAckReverse to determine when it is permitted to drive the data bus. W83627DHG-P/W83627DHG-PT DESCRIPTION DESCRIPTION acknowledge nReverseRequest. Publication Release Date: July 09, 2009 -168- The ...
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... The most significant bits of the command indicate whether run-length count (for compression channel address. In the reverse direction, normal data are transferred when PeriphAck is high, and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. W83627DHG-P/W83627DHG-PT DESCRIPTION Publication Release Date: July 09, 2009 -169- ...
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... Data Compression The W83627DHG-P hardware supports RLE decompression and can transfer compressed data to a peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to ecpDFifo. 13.3.13 FIFO Operation The FIFO threshold is set in LD0 CRO0, bit ...
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... KEYBOARD CONTROLLER The W83627DHG-P KBC (8042 with licensed KB BIOS) circuit is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse and can be used with IBM compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
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... Disable Keyboard 3 Reserve System Flag 2 1 Enable Auxiliary Interrupt 0 W83627DHG-P/W83627DHG-PT DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset ...
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... W83627DHG-P/W83627DHG-PT COMMAND A4h Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded A5h Load Password Load Password until a logical 0 is received from the system A6h Enable Password Enable the checking of keystrokes for a match with the password A7h Disable Auxiliary Device Interface ...
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... KBRESET depending on received data bit 0. When the KBC receives an "FE" command, the KBRESET is pulse low for 6μs (Min.) with a 14μs (Min.) delay. GATEA20 and KBRESET are controlled by either software or hardware logic, and they are mutually exclusive. Then, GATEA20 and KBRESET are merged with Port92 when the P92EN bit is set. W83627DHG-P/W83627DHG- ...
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... Drives GATE A20 signal to high. 0: Drives GATE A20 signal to low. 0 PLKBRST#. Pull-Low KBRESET. A logical 1 on this bit causes KBRESET to drive low for 6 μS (Min.) with a 14 μS (Min.) delay. Before issuing another keyboard-reset command, the bit must e cleared. W83627DHG-P/W83627DHG- Res. (0) Res. (1) ...
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... Logical Device A, CR [F2h], bit [0] and is for enabling or disabling the PME function. If this bit is set to “0”, the W83627DHG-P won’t output any PME signal when any of the wake-up events has occurred and is enabled. The four registers are divided into PME status registers and PME ...
Page 187
... Power Control Logic This chapter describes how the W83627DHG-P implements its ACPI function via these power control pins: PSIN# (Pin 68), PSOUT# (Pin 67), SUSB# (i.e. SLP_S3#; Pin 73) and PSON# (Pin 72). The following figure illustrates the relationships. PSON# PSON# PSON# PSON# 3VSB/VBAT ...
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... By definition, AC power failure means that the standby power is removed. The power failure resume control logic of the W83627DHG-P is used to recover the system to a pre-defined state after AC power failure. Two control bits at Logical Device A, CR [E4h], bits [6:5] indicate the pre-defined state. The ...
Page 189
... To ensure that VCC does not fall faster than VSB in various ATX Power Supplies, the W83627DHG-P adds the option of “user define mode” for the pre-defined state before AC power failure. BIOS can set the pre-defined state to be “On” or “Off”. According to this setting, the system is returned to the pre-defined state after the AC power recovery ...
Page 190
... Three control bits (ENMDAT_UP, MSRKEY, MSXKEY) define the combinations of the mouse wake-up events. Please see the following table for the details. Table 15-2 Definitions of Mouse Wake-Up Events ENMDAT_UP MSRKEY (LOGICAL DEVICE A, (LOGICAL DEVICE A, CR[E6H], BIT 7) CR[E0H], BIT W83627DHG-P/W83627DHG- First-pressed key “0” Second-pressed key “1” Third-pressed key “2” MSXKEY (LOGICAL ...
Page 191
... The RSMRST# (Pin 75) signal is a reset output and is used as the 3VSB power-on reset signal for the South Bridge. When the W83627DHG-P detects the 3VSB voltage rises to “V1”, it then starts a delay – “t1” before the rising edge of RSMRST# asserting. If the 3VSB voltage falls below “V2”, the RSMRST# de-asserts immediately ...
Page 192
... Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by programming Logical Device A, CR [E6h], bit 3 to “1”. Furthermore, the W83627DHG-P provides four different extra delay time of PWROK for various demands. The four extra delay time are designed at Logical Device A, CR [E6h], bits 2~1 ...
Page 193
... ATXPGD is active during t2, so PWROK and PWROK2 assert after t2. The timing of t2 starts when 3VCC voltage rises to “V3”. No matter the ATXPGD signal activation is during or after t2, PWROK and PWROK2 assert or de-assert according to the 3VCC voltage and the ATXPGD signal. W83627DHG-P/W83627DHG- ...
Page 194
... ATXPGD are valid t2 PWROK/PWROK2 (output) Timing and voltage parameters are shown in the following table. SYMBOL PARAMETER V3 3VCC Valid Voltage 3VCC Ineffective Voltage V4 Starting from valid 3VCC t2 W83627DHG-P/W83627DHG-PT V4 Figure 15-9 MIN. TYP. 2.4 2.6 2.25 2.4 300 - Publication Release Date: July 09, 2009 -184- ...
Page 195
... There are two modes of operation for the SERIRQ Start Frame: Quiet mode and Continuous mode. In the Quiet mode, the W83627DHG-P drives the SERIRQ signal active low for one clock, and then tri- states it. This brings all the state machines of the W83627DHG-P from idle to active states. The host controller (the South Bridge) then takes over driving SERIRQ signal low in the next clock and continues driving the SERIRQ low for programmable clock periods ...
Page 196
... If the corresponding IRQ is inactive, then SERIRQ must be left tri-stated. During the Recovery phase, the W83627DHG-P device drives the SERIRQ high. During the Turn-around phase, the W83627DHG- P device leaves the SERIRQ tri-stated. The W83627DHG-P starts to drive the SERIRQ line from the beginning of "IRQ0 FRAME" based on the rising edge of PCICLK. ...
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... None IRQ15 H=Host Control R=Recovery Note: 1. There may be none, one or more Idle states during the Stop Frame. 2. The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the turn-around clock of the Stop Frame. W83627DHG-P/W83627DHG-PT IOCHCK# STOP FRAME FRAME ...
Page 198
... Watchdog Timer function. Writing any non-zero value to this register causes the counter to load this value into the Watchdog Timer counter and start counting down. The W83627DHG-P outputs a low signal to the WDTO# pin (pin 77) when a time-out event occurs. In other words, when the value is counted down to zero, the timer stops, and the W83627DHG-P sets the WDTO# status bit in Logical Device 8, CR [F7h], bit [4], outputting a low signal to the WDTO# pin (pin 77) ...
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... GENERAL PURPOSE I/O The W83627DHG-P provides 40 input/output ports that can be individually configured to perform a simple basic I/O function or alternative, pre-defined function. GPIO port 6 is configured through control registers in Logical Device 7, and GPIO ports Logical Device 9. Users can configure each individual port input or output port by programming respective bit in selection register (0 = output input) ...
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... VID INPUTS AND OUTPUTS The W83627DHG-P provides eight pins for VID input or output function. The default function is VID input. These pins can be configured to VID output function by setting Logical Device B, CR [F0h], bit The configuration is applied to the 8 pins as a group. None of them can be individually set to input or output ...