CDP68HC68P1M96 Intersil, CDP68HC68P1M96 Datasheet - Page 2

• Manufacturer Part Number: CDP68HC68P1M96
• Manufacturer: Intersil

Specifications of CDP68HC68P1M96

• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant

Pin Descriptions
ID
The 4 possible combinations of these pins allow 4 I/Os to
share a common chip enable. When the levels at these pins
match those of the identify bits in the control word, the serial
bus is enabled. The chip identify pins will retain their
previous logic state if the lines driving them become Hi-Z.
MISO - Master-in, Slave out pin. Data bytes are shifted out
at this pin most significant bit first. When the chip enable
signal is high, this pin is Hi-Z.
MOSI - Master-out, Slave in pin. Data bytes are shifted in at
this pin most significant bit first. This pin will retain its
previous logic state if its driving line becomes Hi-Z.
0
, ID
1
- Chip identify pins, normally tied to V
2
SCK
MOSI
ID
ID
CE
DATA OUT
1
0
ENABLE
DATA IN
CLOCK
DIRECTION
REGISTER
CHIP
FIGURE 1. SINGLE PORT I/O BLOCK DIAGRAM
DD
to V
FIGURE 2. SINGLE PORT I/O
SS
CDP68HC68P1
CE
MOSI
MISO
SCK
.
CDP68HC68P1
SHIFT REGISTER
INPUT/OUTPUT
COMPARATOR
CONTROL
LOGIC
D0 - D7
ID
ID
D0 - D7
SCK - Serial clock input. This input causes serial data to be
latched from the MOSI input and shifted out on the MISO
output.
CE - A negative chip enable input. A high to low transition on
this pin latches the inactive SCK polarity and compare flag
and indicates the start of a data transfer. The serial interface
logic is enabled only when CE is low. This pin will retain its
previous logic state if its driving line becomes Hi-Z.
D0 -D7 - I/O Port pins. Individual programmable inputs or
outputs.
V
All pins except the power supply lines and MISO have
Schmitt-trigger buffered inputs.
0
1
DD
and V
I/O PORT
SS
CHIP
IDENTIFY
- Positive and negative power supply line.
DIRECTION
REGISTER
DATA
IN/OUT
MISO