AM53CF96KC/W AMD (ADVANCED MICRO DEVICES), AM53CF96KC/W Datasheet - Page 17

• Manufacturer Part Number: AM53CF96KC/W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM53CF96KC/W

• Lead Free Status / RoHS Status: Not Compliant

Current Transfer Count Register
(00H, 01H, 0EH) Read Only
CTCREG – Bits 23:0 – CRVL 23:0 – Current
Value 23:0
This is a three-byte register which decrements to keep
track of the number of bytes transferred during a DMA
transfer. Reading these registers returns the current
value of the counter. The counter will decrement by one
for every byte and by two for every word transferred. The
transaction is complete when the count reaches zero,
and bit 4 of the Status Register (04H) is set. Should the
sequence terminate early, the sum of the values in the
Current FIFO (07H) and the Current Transfer Count
Register reflect the number of bytes remaining.
The least significant byte is located at address 00H, the
middle byte is located at address 01H, and the most sig-
nificant byte is located at address 0EH. Register 0EH
extends the total width of the register from 16 to 24
bits, and is only enabled when the Enable Features
bit (bit 6) of Control Register Two is set to a value
of ‘1’.
These registers are automatically loaded with the val-
ues in the Start Transfer Count Register every time a
DMA command is issued. However, following a chip or
power on reset, up until the time register 0EH is loaded,
the Am53CF94/96’s part-unique ID can be obtained by
reading register 0EH.
In the Target mode, this counter is decremented by the
active edge of DACK during the Data-In phase and by
REQC during the Data-Out phase.
Current Transfer Count Register
CTCREG
CRVL15
CRVL23 CRVL22 CRVL21
CRVL7
23
15
7
x
x
x
CRVL14
CRVL6
22
14
6
x
x
x
CRVL13 CRVL12 CRVL11 CRVL10
CRVL5
21
13
5
x
x
x
CRVL4
CRVL20 CRVL19 CRVL18
20
12
x
x
4
x
CRVL3
19
11
x
x
3
x
CRVL2
18
10
Address: 00
2
x
x
x
CRVL9
CRVL1
CRVL17 CRVL16
17
9
1
x
x
x
Type: Read
17348B-16
Am53CF94/Am53CF96
H,
01
CRVL0
CRVL8
16
8
0
H, 0EH
x
x
x
In the Initiator mode, the counter is decremented by the
active edge of DACK during the Synchronous Data-In
phase or by ACKC during the Asynchronous Data-In
phase and by DACK during the Data-Out phase.
Start Transfer Count Register
(00H, 01H, 0EH) Write Only
STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0
This is a three-byte register which contains the number
of bytes to be transferred during a DMA operation. The
value in the Start Transfer Count Register must be pro-
grammed prior to command execution.
The least significant byte is located at address 00H, the
middle byte is located at address 01H, and the most sig-
nificant byte is located at address 0EH. Register 0EH
extends the total width of the register from 16 to 24 bits,
and is only enabled when the Enable Features bit (bit 6)
of Control Register Two is set to a value of ‘1’. This sets
the maximum transfer count to 16.78 MBytes. When a
value of ‘0’ is written to these registers, the transfer
count will be set to the maximum. A DMA NOP com-
mand must be issued before the transfer counter values
can be written to 00H, 01H, and 0EH.
These registers retain their value until overwritten, and
are therefore unaffected by a hardware or software re-
set. This reduces programming redundancy since it is
no longer necessary to reprogram the count for subse-
quent DMA transfers of the same size.
Start Transfer Count Register
STCREG
STVL15 STVL14 STVL13 STVL12 STVL11 STVL10
STVL23
STVL7
23
15
x
x
7
x
STVL6
STVL22
22
14
6
x
x
x
STVL5
STVL21 STVL20 STVL19
21
13
5
x
x
x
STVL4
12
20
4
x
x
x
STVL3
11
19
3
x
x
x
STVL2
STVL18
10
18
2
x
x
x
Address: 00
STVL9
STVL1
STVL17 STVL16
9
1
x
x
17
x
Type: Write
17348B-17
AMD
STVL8
STVL0
8
x
0
x
16
H–
x
01
17
H