LSISAS1068E LSI, LSISAS1068E Datasheet - Page 14

• Manufacturer Part Number: LSISAS1068E
• Manufacturer: LSI

Specifications of LSISAS1068E

• Lead Free Status / RoHS Status: Not Compliant

I
Memory Interface Signals
14 of 30
DB08-000274-03
2
C and UART Signals
TX[7:0]+
This section describes the I
ISTWI_CLK
ISTWI_DATA I
UART_RX
UART_TX
This section describes the memory interface signals.
MCLK
ADSC/
ADV/
MAD[31:0]
MADP[3:0]
LSISAS1068E PCI Express to 8-Port Serial Attached SCSI Controller
October 2006 - Version 2.1
Multiplexed Address/Data
Transmit Positive Differential Data
TX[x]+ provides the positive differential data transmit
signal for SAS/SATA phy[x].
I
This signal provides the I
This signal provides the I
UART Receive
This signal provides the UART receive signal.
UART Transmit
This signal provides the UART transmit signal.
Memory Clock
All synchronous RAM control/data signals reference the
rising edge of this clock.
Address-Strobe-Controller
Asserting this active LOW signal initiates read, write, or
chip deselect cycles.
Advance
Asserting this active LOW signal increments the burst
address counter of the selected synchronous SRAM.
These signals provide the address and data bus for the
PBSRAM, flash ROM, and NVSRAM. These signals also
provide Power-On Sense configuration functions to the
LSISAS1068E. These signals are internally pulled LOW.
Memory Parity
These signals provide parity checking for MAD[31:0].
These signals are internally pulled HIGH.
2
2
C Clock
C Data
Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
2
C and UART signals.
2
2
C clock signal.
C data signal.
Input/Output
Input/Output
Input/Output
Input/Output
Output
Output
Output
Output
Output
Input