LT4430ES6#PBF Linear Technology, LT4430ES6#PBF Datasheet - Page 10

• Manufacturer Part Number: LT4430ES6#PBF
• Manufacturer: Linear Technology

Specifications of LT4430ES6#PBF

• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Pin Count: 6
• Mounting: Surface Mount
• Package Type: TSOT-23
• Case Length: 2.9mm
• Screening Level: Automotive
• Lead Free Status / RoHS Status: Compliant

LT4430
APPLICATIONS INFORMATION
If the fault condition ceases, the output voltage increases.
In response, the error amplifi er COMP pin’s voltage
decreases. This action opens switch S1, deactivates the
overshoot control amplifi er and allows the OC pin capacitor
to charge. The FB pin voltage increases quickly until the
FB pin voltage exceeds the OC pin voltage. The feedback
loop increases the drive to the opto-coupler until the FB
pin follows and regulates to the OC pin voltage. Again, as
the OC pin voltage increases past 600mV, the reference
voltage takes control of the error amplifi er and the FB pin
regulates to 600mV.
Generating a V
Biasing an LT4430 is crucial to proper operation. If the
overshoot control (OC) function is not being used and the
output voltage is greater than 3.3V, the IC may be biased
from V
verify large-signal start-up and fault recovery behavior.
If the overshoot control function is being used or the
output voltage is below the LT4430’s minimum operat-
ing voltage of 3V, employing an alternate bias method is
necessary. The LT4430’s undervoltage lockout (UVLO)
circuitry, controlled by V
capacitor low for V
above 2.2V, the circuit releases the OC pin capacitor. The
LT4430’s supply voltage must come up faster than the
output voltage to assert loop control and limit output volt-
age overshoot. In most cases, a few simple components
accomplish this task. Adding a few biasing components
to control overshoot is advantageous. Let’s examine bias
circuits for different topologies.
10
OUT
. In these cases, it is the user’s responsibility to
IN
Bias Supply
IN
less than 2.2V. When V
IN
, resets and holds the OC pin
IN
increases
Figures 1a to 1e illustrate bias supply circuits for the
fl yback converter. Figure 1a shows the typical fl yback
output connection. Figures 1b and 1c exhibit equivalent
circuit performance but rotate the rectifi er connection to
the ground-referred side. This connection permits the user
to take advantage of the transformer secondary’s forward
behavior when the primary-side switch is on.
Figures 1d to 1e illustrate the bias generator circuit.
V
the primary-side switch is on. D2 forward biases and
C1 charges. During this time, the secondary-voltage is
in series with V
N + V
V
C1 is generally much smaller in value than C
bias supply starts up ahead of V
1e limits peak charging currents, lowering D2’s current
rating. R1 also fi lters C1 from peak-charging to the volt-
age spikes induced by the secondary winding’s leakage
inductance. Between 1Ω to 10Ω is generally suffi cient. R1
is usually necessary if C1 is a low ESR ceramic capacitor
or if the transformer has high leakage inductance. It may
be possible to eliminate R1 if C1 is a low cost, high ESR,
surface-mount tantalum.
V
ing on V
the bias supply may exceed the LT4430’s 20V V
maximum rating. If this occurs, two solutions exist. One
is to tap the secondary-side inductor to create a lower
voltage from which to rectify as illustrated in Figure 2a.
The bias voltage decreases to (V
This solution relies on secondary-side pins being available
for the tap point.
IN
OUT
IN
variation changes the bias supply in Figure 1d. Depend-
• N volts appear across the secondary winding when
is zero at start-up, V
OUT
OUT
– V
, the transformer turns ratio N and V
F
). V
OUT
F
is the forward voltage of D2. When
and C1 ultimately charges to (V
IN
• N volts exists to charge C1.
OUT
IN
. R1 in Figures 1d and
• N1/N + V
OUT
IN
OUT
IN
absolute
and the
range,
– V
4430fa
IN
F
).
•