LTC2951CTS8-2#PBF Linear Technology, LTC2951CTS8-2#PBF Datasheet - Page 9

• Manufacturer Part Number: LTC2951CTS8-2#PBF
• Manufacturer: Linear Technology

Specifications of LTC2951CTS8-2#PBF

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 8
• Mounting: Surface Mount
• Package Type: TSOT-23
• Case Length: 2.9mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Compliant

APPLICATIO S I FOR ATIO
Description
The LTC2951 is a low power (6µA), wide input voltage range
(2.7V to 26.4V), push button On/Off controller that can
interface to a µP and a power supply. The part incorporates
all the fl exible timing needed to debounce the push button
input ( ⎯ P ⎯ B ). The LTC2951 also provides a simple interface
( ⎯ I ⎯ N ⎯ T output, ⎯ K ⎯ I ⎯ L ⎯ L input) to allow a system to power on and
power off in a controlled manner. The wide input voltage
range allows a system designer to operate from single cell
to multi-cell battery stacks. Very low quiescent current
makes the LTC2951 ideal for continuously monitoring the
On/Off push button of a handheld device.
Turn On
When power is fi rst applied to the LTC2951, the part initial-
izes the output pins. Any DC/DC converters connected to
the EN/ ⎯ E ⎯ N pin will therefore be off. To assert the enable
output, ⎯ P ⎯ B must be held low for a minimum of 128ms
(t
Once the enable output is asserted, any DC/DC converters
connected to this pin are turned on. The ⎯ K ⎯ I ⎯ L ⎯ L input from
the µP is ignored during the succeeding 512ms blanking
time (t
maximum time required to power up the DC/DC converter
and the µP. If ⎯ K ⎯ I ⎯ L ⎯ L is not brought high during this 512ms
time window, the enable output is released. The assump-
tion is that 512ms is suffi cient time for the system to
power up.
Turn Off
To initiate a power off sequence, ⎯ P ⎯ B must be held low for a
minimum of 32ms (t
time may be added via an optional capacitor connected to
the OFFT pin (t
additional time that ⎯ P ⎯ B must be held low to initiate a power
off sequence. C
Once ⎯ P ⎯ B has been validly pressed, ⎯ I ⎯ N ⎯ T is switched low.
This alerts the µP to perform its power down and house-
keeping tasks.
DB
C
OFFT
,
ON
⎯ K ⎯ I ⎯ L ⎯ L
).
= 1.56E-4 [μF/ms] • (t
,
ON BLANK
OFFT
OFFT
). The following equation describes the
U
DB
is the OFFT external capacitor:
). This blanking time represents the
,
OFF
U
). Additional turn off debounce
OFFT
– 1ms)
W
U
⎯ K ⎯ I ⎯ L ⎯ L Turn Off Delay
The LTC2951 provides a failsafe feature that allows the
user to turn off system power (via ⎯ P ⎯ B ) under system fault
conditions. During a normal power down sequence, the
LTC2951 fi rst interrupts the µP by setting ⎯ I ⎯ N ⎯ T low. The
µP then performs power down and housekeeping tasks
and drives ⎯ K ⎯ I ⎯ L ⎯ L low when done. The LTC2951 releases the
enable output, thus turning off system power. The ⎯ K ⎯ I ⎯ L ⎯ L
turn off timer starts when ⎯ I ⎯ N ⎯ T is driven low. If the µP fails
to respond during this timeout period, the enable output
will automatically release. The default power down timeout
period is 128ms (t
by placing an optional capacitor on the KILLT pin (t
OFF DELAY, ADDITIONAL
the additional power down timeout period. C
KILLT external capacitor:
C
Note that ⎯ K ⎯ I ⎯ L ⎯ L can be driven low (thereby releasing the
enable output) at any time after t
Simplifi ed Power On/Off Sequence
Figure 1 shows a simplifi ed LTC2951-1 power on and power
off sequence. A high to low transition on ⎯ P ⎯ B (t
the power on sequence. This diagram does not show any
bounce on ⎯ P ⎯ B . In order to assert the enable output, the ⎯ P ⎯ B
pin must stay low continuously ( ⎯ P ⎯ B high resets timers) for
128ms (t
blanking timer is started. This blanking timer is designed
to give suffi cient time for the DC/DC converter to reach its
fi nal voltage, and to allow the µP enough time to perform
power on tasks.
The ⎯ K ⎯ I ⎯ L ⎯ L pin must be pulled high within 512ms of the
EN pin going high. Failure to do so results in the EN
pin going low 512ms after it went high. (EN = low, see
Figure 2). Note that the LTC2951 does not sample ⎯ K ⎯ I ⎯ L ⎯ L
and ⎯ P ⎯ B until after the 512ms internal timer has expired.
The reason ⎯ P ⎯ B is ignored is to ensure that the system
is not forced off while powering on. Once the 512ms
timer expires (t
debounced with an internal 32ms timer. The system has
now properly powered on and the LTC2951 monitors ⎯ P ⎯ B
KILLT
= 1.56e-4 [µF/ms] • (t
2
–t
1
LTC2951-1/LTC2951-2
). Once EN goes high (t
4
), the release of the ⎯ P ⎯ B pin is then
⎯ K ⎯ I ⎯ L ⎯ L
). The following equation describes
,
OFF DELAY
⎯ K ⎯ I ⎯ L ⎯ L
,
OFF DELAY, ADDITIONAL
), which can be extended
⎯ K ⎯ I ⎯ L ⎯ L
2
,
), an internal 512ms
ON BLANK
KILLT
1
period.
) initiates
– 1ms)
is the
295112fa
⎯ K ⎯ I ⎯ L ⎯ L
9
,