TLE8203EXT Infineon Technologies, TLE8203EXT Datasheet - Page 12

• Manufacturer Part Number: TLE8203EXT
• Manufacturer: Infineon Technologies

Specifications of TLE8203EXT

• Operating Temperature (max): 150C
• Operating Temperature (min): -40C
• Pin Count: 36
• Mounting: Surface Mount
• Screening Level: Automotive
• Lead Free Status / RoHS Status: Supplier Unconfirmed

7
7.1
The SPI is used for bidirectional communication with a control unit. The TLE 8203E acts as SPI-slave and the
control unit acts as SPI-master. The 16-bit control word is read via the DI serial data input. The status word
appears synchronously at the DO serial data output. The communication is synchronized by the serial clock input
CLK.
Standard data transfer timing is shown in
low during CSN transition. The transfer is MSB first.
The transmission cycle begins when the chip is selected with the chip-select-not (CSN) input (H to L). Then the
data is clocked through the shift register. The transmission ends when the CSN input changes from L to H and the
word which has been read into the shift register becomes the control word. The DO output switches then to tristate
status, thereby releasing the DO bus circuit for other uses. The SPI allows to parallel multiple SPI devices by using
multiple CSN lines. The SPI can also be used with other SPI-devices in a daisy-chain configuration.
Figure 3
7.2
The 16-bit SPI frame is composed of an addressable block, an address-independent block and a 2-bit address as
shown in
The control word transmitted from the master to the TLE 8203E is executed at the end of the SPI transmission
(CSN L -> H) and remains valid until a different control word is transmitted or a power on reset occurs. At the
beginning of the SPI transmission (CSN H -> L), the diagnostic data currently valid are latched into the SPI and
transferred to the master. For Status Register address handling, please refer to
Final Data Sheet
CLK
CSN
DO
Figure
DI
SPI
General
SPI Standard Data Transfer Timing
Register Address
4.
CSN High to Low & rising edge of SCLK: SDO is enabled. Status information is transfered to Output Shift Register
EF
15 14 13 12 11 10
CSN Low to High: Data from Shift-Register is transfered to Output Driver Logic
15
15
14
14
13
13
SDO: State will change on the rising edge of CLK-Signal
SDI: Data will be accepted on the falling edge of CLK-Signal
12
12
11
11
10
10
Figure
9
9
9
previous Status
actual Data
8
8
8
3. The clock polarity is data valid on falling edge. CLK must be
7
7
7
12
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
Section
7.4.
actual Status
15
15
new Data
Rev. 1.0, 2009-02-04
15 14
14
14
TLE 8203E
time
SPI