ML4824CS2_NL Fairchild Semiconductor, ML4824CS2_NL Datasheet - Page 11

• Manufacturer Part Number: ML4824CS2_NL
• Manufacturer: Fairchild Semiconductor

Specifications of ML4824CS2_NL

• Start-up Supply Current: 700uA
• Switching Freq: 81kHz
• Operating Supply Voltage (min): 12.8V
• Operating Supply Voltage (typ): 13.5V
• Operating Supply Voltage (max): 14.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: SOIC W
• Pin Count: 16
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

PRODUCT SPECIFICATION
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
REV. 1.0.6 11/7/03
+
DC
+
DC
VIN
VIN
OSC
OSC
REF
REF
I1
I1
L1
U4
L1
U4
+
–
+
–
EA
RAMP
CLK
EA
RAMP
CLK
U3
U3
Figure 5. Typical Leading Edge Control Scheme.
Figure 4. Typical Trailing Edge Control Scheme.
VEAO
SW2
SW2
SW1
SW1
+
–
+
–
U1
CMP
U1
I2
I2
C1
C1
I4
I4
I3
I3
R
D
R
D
DFF
DFF
CLK
CLK
U2
U2
RL
RL
Q
Q
Q
Q
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple
voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the first stage
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
RAMP
RAMP
VSW1
VSW1
VEAO
VEAO
TIME
TIME
TIME
TIME
ML4824
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