MCIMX351AJQ5C Freescale, MCIMX351AJQ5C Datasheet - Page 146

• Manufacturer Part Number: MCIMX351AJQ5C
• Manufacturer: Freescale

Specifications of MCIMX351AJQ5C

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

146
Revision
Number
6
5
4
1
0
10/21/2009 • Added information for silicon rev. 2.1
08/06/2009 • Filled in TBDs in
04/30/2009 Note: There were no revisions of this document between revision 1 and revision 4.
12/2008
10/2008
Date
Initial public release
• Updated
• Added
• Added
• Revised
• Added
• In
• Updated values in
• Added
• In
• In
• In
• Updated Section 4.3.1, “Powering Up.”
• Section 4.7, “Module-Level AC Electrical Specifications”: Updated NFC, SDRAM and mDDR
(1.8 V).”
Modes),”
Type IO Pins in mDDR Mode,”
SDRAM Mode,”
Memory Timing Diagram for Read Access—WSC = 1,”
Diagram for Synchronous Read Access— WSC = 7, LBA = 1, LBN = 1, LAH = 1, OEA = 7.”
Figure 37, “ESAI Transmitter Timing,”
signals. Removed a note from
SDRAM timing. Inserted DDR2 SDRAM timing.
i.MX35 Applications Processors for Automotive Products, Rev. 9
Table 95. i.MX35 Data Sheet Revision History (continued)
Section 4.3.1, “Powering
Section 4.8.2, “AC Electrical Characteristics for DDR Pins (DDR2, Mobile DDR, and SDRAM
Section 4.9.5.2, “Wireless External Interface Module (WEIM),”
Section 4.9.6, “Enhanced Serial Audio Interface (ESAI) Timing Specifications,”
Table
Table
Table
Section 4.4, “Reset Timing.”
Figure 15
Table
removed Slow Slew rate tables, relabeled
92, “Silicon Revision 2.1 Signal Ball Map Locations.”
94, “Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch.”
25, “AC Electrical Characteristics of DDR Type IO Pins in SDRAM Mode Max Drive
1, “Ordering Information.”
to exclude mention of slew rate.
Table
Table 10, “i.MX35 Power Modes.”
and
14.
Table 31
Up,” reverse positions of steps
Figure 37, “ESAI Transmitter Timing.”
and
by removing FCE = 0 and FCE = 1. Added footnote 3 to the table.
Table 24, “AC Electrical Characteristics of DDR Type IO Pins in
Substantive Change(s)
and
Figure 38, “ESAI Receiver Timing,”
Table 23, “AC Electrical Characteristics of DDR
through
5
and 6.
Figure 21, “Muxed A/D Mode Timing
modified
Figure 16, “Synchronous
Freescale Semiconductor
to remove extraneous
modified