TS68EN360MRB/Q33L E2V, TS68EN360MRB/Q33L Datasheet - Page 2

• Manufacturer Part Number: TS68EN360MRB/Q33L
• Manufacturer: E2V

Specifications of TS68EN360MRB/Q33L

• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Lead Free Status / RoHS Status: Compliant

The term “quad” comes from the fact that there are four serial communications controllers (SCCs) on the device; however,
there are actually seven serial channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral
interface (SPI).
Screening/Quality
This product is manufactured in full compliance with:
•
•
1. Introduction
1.1
2
QML (class Q)
or according to e2v standards
QUICC Architecture Overview
0886C–HIREL–04/08
The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other
members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB). The TS68302 is an
exception, having an 68000 bus on chip. The IMB provides a common interface for all modules of the
TS68300 family, which allows the development of new devices more quickly by using the library of exist-
ing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC
is the first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module
utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in
Figure 1-1.
QUICC Block Diagram
IDMAs
TWO
CPU32+
CORE
FOURTEEN SERIAL
CHANNELS
CONTROLLER
SERIAL
SEVEN
DMAs
RISC
COMMUNICATIONS PROCESSOR
TIMER SLOT
ASSIGNER
IMB (32 BIT)
CPM
CONTROLLER
DUAL-PORT
INTERRUPT
GENERATION
PROTECTION
2.5-KBYTE
FEATURES
PERIODIC
SYSTEM
CLOCK
OTHER
RAM
TIMER
FEATURES
OTHER
SIM 60
CHIP SELECTS
BREAKPOINT
CONTROLLER
INTERFACE
GENERAL-
EXTERNAL
PURPOSE
LOGIC
TIMERS
FOUR
DRAM
JTAG
AND
BUS
Figure
SYSTEM
e2v semiconductors SAS 2008
I/F
1-1.
TS68EN360