CP3UB26G18NEPX National Semiconductor, CP3UB26G18NEPX Datasheet - Page 82
CP3UB26G18NEPX
Manufacturer Part Number
CP3UB26G18NEPX
Description
Manufacturer
National Semiconductor
Datasheet
1.CP3UB26G18NEPX.pdf
(270 pages)
Specifications of CP3UB26G18NEPX
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number:
CP3UB26G18NEPX
Manufacturer:
Texas Instruments
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10 000
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16.0 Random Number Generator (RNG)
The RNG unit is a hardware “true random” number genera-
tor. When enabled, this unit provides up to 800 random bits
per second. The bits are available for reading from a 16-bit
register.
The RNG unit includes two oscillators which operate inde-
pendently of the System Clock:
! Fast Oscillator—a 24 MHz oscillator which drives a lin-
! Slow Oscillator—an unstable oscillator which drives a
By sampling the pseudorandom bitstream at random inter-
vals, a random bitstream is synthesized. This bitstream is
clocked into a 16-bit shift register. A programmable clock di-
vider generates the clock signal for the shift register from the
System Clock.
ear feedback shift register (LFSR).
flip-flop for sampling the pseudorandom bitstream from
the LFSR. This oscillator operates at approximately 115
kHz, but it does not have a fixed frequency.
Figure 18. RNG Module Block Diagram
82
When a new 16-bit word of random data is available, it is
loaded into the RNGD register. If enabled, an interrupt re-
quest (IRQ3) is asserted when the word is available for
reading. When software reads the RNGD register, the reg-
ister is cleared and the interrupt request is deasserted.
The RNGCST register provides control and status bits for
the RNG module:
! RNG Enable—enables or disables the RNG oscillators.
! Interrupt Mask—enables or disables the interrupt when
! Data Valid—indicates whether a new word is available.
16.1
The RNG module provides support for an In-System Emu-
lator by means of a special FREEZE input. When FREEZE
is asserted, the automatic clear-on-read function of the
RNDGD register is disabled.
a new word of random data becomes available.
FREEZE
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