PCA9600DP-T NXP Semiconductors, PCA9600DP-T Datasheet - Page 17

PCA9600DP-T

Manufacturer Part Number
PCA9600DP-T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9600DP-T

Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TSSOP
Pin Count
8
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
PCA9600_4
Product data sheet
Fig 18. I
SDA
SCL
2
C-bus multipoint application
3.3 V to 5 V
3.3 V to 5 V
SX
SY
There is an Excel calculator which makes it easy to determine the maximum I
speed when using the PCA9600. The calculator and instructions can be found at
www.nxp.com/clockspeedcalculator.
PCA9600
The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+
500 ns requirement. This system requires the bus LOW period, and therefore cycle
time, to be increased by 33 ns so the system must run slightly below the 1 MHz limit.
The possible maximum speed has a cycle period of 1033 ns or 968 kHz.
12 V
RX
RY
TX
TY
12 V
12 V
Rev. 04 — 11 November 2009
no limit to the number of connected bus devices
SX
PCA9600
SCL/SDA
SY
SX
PCA9600
SCL/SDA
SY
SX
PCA9600
SCL/SDA
SY
PCA9600
Dual bidirectional bus buffer
3.3 V 3.3 V
twisted-pair telephone wires,
USB, or flat ribbon cables;
up to 15 V logic levels,
include V
CC
PCA9600
© NXP B.V. 2009. All rights reserved.
and GND
SY SDA
SX SCL
2
C-bus clock
001aai065
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