PC8349MTPYALFB E2V, PC8349MTPYALFB Datasheet
PC8349MTPYALFB
Specifications of PC8349MTPYALFB
Related parts for PC8349MTPYALFB
PC8349MTPYALFB Summary of contents
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... MHz (V DD ™ technology with system logic for networking, storage, and = –55° +125° –40° +110° 1.2V) DD 73, for silicon revision level determination. Visit our website: www.e2v.com for the latest version of the datasheet PC8349/E 1037A–HIREL–06/10 ...
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... Core 32-Kbyte L1 Coherent System Bus Instruction Cache 64/32b PCI Controller 0/32b PCI Controller DMA Controller TSEC MII, GMII, TBI, RTBI, RGMII 10/100/1Gb TSEC MII, GMII, TBI, RTBI, RGMII 10/100/1Gb e2v semiconductors SAS 2010 32-Kbyte L1 Data Cache PCI1 PCI2 DMA ...
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... Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): e2v semiconductors SAS 2010 PC8349/E [Preliminary] 1037A–HIREL–06/10 ...
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... External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) • Universal serial bus (USB) multi-port host controller – Can operate as a stand-alone USB host controller – USB root hub with one or two downstream-facing ports 4 1037A–HIREL–06/10 e2v semiconductors SAS 2010 ...
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... Concurrent execution across multiple channels with programmable bandwidth control – Handshaking (external control) signals for all channels: DMA_DREQ[0:3], DMA_DACK[0:3], DMA_DDONE[0:3] – All channels accessible to local core and remote PCI masters – Misaligned transfer capability – Data chaining and direct mode e2v semiconductors SAS 2010 2 C interfaces 2 C mode support 2 ...
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... V for 667-MHz core DD frequency) – 0.3 to 1.32 (1.36 max AV for 667-MHz core DD frequency) – 0 – 0.3 to 1.98 – LV 0.3 to 3.63 DD – OV 0.3 to 3.63 DD Unit Notes V – V – V – V – V – e2v semiconductors SAS 2010 ...
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... Three-speed Ethernet I/O supply voltage PCI, local bus, DUART, system control and power management, I Note the positive or negative direction. e2v semiconductors SAS 2010 (1) (Continued and JTAG signals must not exceed GV by more than 0.3V. This limit can be exceeded for a maximum of IN ...
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... PCI interface of the PC8349 (Min) Overvoltage Waveform 4 ns (Max) Undervoltage Waveform /OV / (1) +7.1V 7.1V p-to-p (Min (Max) 62.5 ns +3.6V 7.1V p-to-p (Min) -3.5V e2v semiconductors SAS 2010 ...
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... I/O pins are three-stated. To minimize the time that I/O pins are actively driven rec- ommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up. e2v semiconductors SAS 2010 Output Impedance (Ω) 36 (half strength mode) ...
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... For I/O power values, see 110°C, and a Dhrys 1.2 V, worst case process, a junction temperature of = 110° C, and a Dhrys 1.3 V, worst case process, a junction temperature of e2v semiconductors SAS 2010 (4) Unit ...
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... MHz, 32 bits 133 MHz, 32 bits 83 MHz, 32 bits Local bus I/O load = MHz, 32 bits 50 MHz, 32 bits TSEC I/O load = 25 pF GMII or TBI RGMII or RTBI 12 MHz USB 480 MHz Other I/O e2v semiconductors SAS 2010 (1.8 V) (2.5 V) 0.31 0.42 0.42 0.55 0.35 0.5 ...
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... CLKIN – – – Symbol Min Max –0.3 0 – ± – ± – ±50 IN Table 4-2 provides the clock input Max Unit 66 MHz – ±150 ps e2v semiconductors SAS 2010 Unit V V µA µA µA Notes (1)(6) – (2) (3) (4)(5) ...
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... PCI_SYNC_IN. In PCI host mode, the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the PC8349/E PowerQUICC™ II Pro Integrated Host Processor Family Refer- ence Manual. e2v semiconductors SAS 2010 Symbol Condition V – ...
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... REF MV +0.125 GV +0.3 REF DD –0.3 MV –0.125 REF –9.9 9.9 –13.4 – 13.4 – at all times variations as measured at the receiver REF ≤ OUT DD e2v semiconductors SAS 2010 Notes (1)(2) 59. (typ) = 1.8V. DD 73, for Unit Notes (1) V ( – V – (4) µA mA – mA – ...
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... Note: 1. This parameter is sampled. GV to-peak) = 0.2 V. Table 6-5 provides the current draw characteristics for MV Table 6-5. Current Draw Characteristics for MV Parameter/Condition Current draw for MV Note: 1. The voltage regulator for MV e2v semiconductors SAS 2010 Symbol = 1.8 V ± 0.090 MHz Symbol REF V TT ...
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... V 5%) ± Min Max Unit ps –600 600 –750 750 –750 750 –750 750 = ± (T/4 – abs (t )); where T is the clock period CISKEW . e2v semiconductors SAS 2010 (typ) = 1.8 V. Notes – – Notes – – Notes (1)(2) (3) – – . DISKEW ...
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... MHz MCS(n) output setup with respect to MCK 400 MHz 333 MHz 266 MHz 200 MHz MCS(n) output hold with respect to MCK 400 MHz e2v semiconductors SAS 2010 illustrates the DDR input timing diagram showing the t t MCK D0 t DISKEW 5%) ± ...
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... DDR DDKHAS memory clock reference (K) goes low (L) until data MCK describes the DDR timing (DD) from the DDKHMH can be modified through control of the DDKHMH DDKHMP e2v semiconductors SAS 2010 Notes (4) (5) (5) (6) (6) (first follows the sym- ...
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... DDR SDRAM output timing diagram. Figure 6-3. DDR SDRAM Output Timing Diagram MCK[n] MCK[n] MODT ADDR/CMD/ MDQS[n] MDQ[x] Figure 6-4 provides the AC test load for the DDR bus. Figure 6-4. DDR AC Test Load e2v semiconductors SAS 2010 DDKHMH MCK[n] MCK[n] t MCK t DDKHMH(max) MDQS t DDKHMH(min) MDQS t ...
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... Subse- th sample. Min Max 0.3 DD –0.3 0.8 – ±5 OV – 0.2 – DD – 0.2 Unit Notes baud baud – Section 8.3 ”Ethernet 29. e2v semiconductors SAS 2010 Unit V V µ (1) (2) ...
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... Parameter Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Note: 1. The symbol page e2v semiconductors SAS 2010 and Table 8-2. The RGMII and RTBI signals in Symbol Conditions ( –4.0 mA ...
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... For example, t clock reference (K) going to the high state (H) GTX clock reference (K) going to the high state GTX t GTXR t GTXF t GTKHDX e2v semiconductors SAS 2010 Max Unit – ns 56.25 % 5.0 ns 1.0 ns 1.0 ns – ...
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... For example, the subscript of t vention is used with the appropriate letter: R (rise (fall). Figure 8-2 shows the GMII receive AC timing diagram. Figure 8-2. GMII Receive AC Timing Diagram RX_CLK RXD[7:0] RX_DV RX_ER e2v semiconductors SAS 2010 /OV of 3.3 V 10%) ± Symbol t GRXH t ...
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... MTXF (first two letters of functional block)(signal)(state)(refer- for outputs. For example, t clock reference (K) going high (H) until data out- MTX represents the MII(M) MTX t MTXR t MTXF t MTKHDX e2v semiconductors SAS 2010 Max Unit – ns – 4.0 ns 4.0 ns MTKHDX ...
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... Figure 8-4 provides the AC test load for TSEC. Figure 8-4. TSEC AC Test Load Figure 8-5 shows the MII receive AC timing diagram. Figure 8-5. MII Receive AC Timing Diagram RX_CLK RXD[3:0] RX_DV RX_ER e2v semiconductors SAS 2010 /OV of 3.3 V ± 10 (min (max (max (min) IH ...
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... For example, t (K) going high (H) until the ref- TTX symbolizes the TBI TTKHDX (K) going high (H) until the referenced data signals TTX represents the TBI TTX t TTXR t TTKHDX e2v semiconductors SAS 2010 Unit – – TTKHDV ...
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... Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0. Figure 8-7 shows the TBI receive AC timing diagram. Figure 8-7. TBI Receive AC Timing Diagram PMA_RX_CLK1 PMA_RX_CLK0 e2v semiconductors SAS 2010 /OV of 3.3 V ± 10 (min (max) IL ...
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... RGT /2. DD (1) Min Typ Max – 0.5 0.5 1.0 – 2.8 7.2 8.0 8 RGT / RGT – 0.75 – – 0.75 (6) – 8 – 53 G125 represents the TBI (T) receive (RX) clock. Also, the RGT e2v semiconductors SAS 2010 Unit – ...
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... Parameter Supply voltage (2.5 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Note: 1. The symbol V 2-2 on page e2v semiconductors SAS 2010 TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] ...
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... For example, t from clock reference (K) high (H) until data MDC symbolizes management data timing (MD) MDDVKH e2v semiconductors SAS 2010 Unit µA µA and Table 2- Notes (2) – – (3) – ...
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... The symbols for timing specifications follow the pattern of t ence)(state) symbolizes USB timing (US) for the input ( invalid (X) with respect to the time the USB clock ref- erence (K) goes high (H). Also high (H), with respect to the output (O) going invalid (X) or output hold time. e2v semiconductors SAS 2010 t MDC MDC t ...
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... AC test load and signals for the USB, respectively 50Ω Output 0 Input Signals t USKHOV Output Signals: Symbol = –100 µ 100 µ 50Ω USIXKH t USIVKH t USKHOX Min Max 0 –0.3 0 – ± –0.2 – – 0.2 OL e2v semiconductors SAS 2010 of the signal DD Unit V V µ ...
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... For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the com- ponent pin is less than or equal to that of the leakage current specification. e2v semiconductors SAS 2010 Table 10-3 describe the general timing parameters of the local bus interface of the ...
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... LBIXKH1 of the signal in question for 3.3 V sig 50Ω L e2v semiconductors SAS 2010 Notes (2) (3)(4) (3)(4) (5) (6) (7) (3) (8) (first LBKHOX ...
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... LAD[0:31]/LDP[0:3] Output (Address) Signal: Figure 10-3. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) LAD[0:31]/LDP[0:3] LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE LAD[0:31]/LDP[0:3] e2v semiconductors SAS 2010 Figure 10-7 on page 38 show the local bus signals. LSYNC_IN Input Signals: Output Signals: t LBKHOV ...
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... UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] 36 1037A–HIREL–06/10 LSYNC_IN LBKHOV1 LCS[0:7]/LWE t LUPWAIT t Input Signals: t LBKHOV1 LCLK LBKLOV LCS[0:7]/LWE LUPWAIT Input Signals: t LBKLOV t LBKHOZ1 t LBIXKH2 LBIVKH2 t LBIXKH1 LBIVKH1 t LBKHOZ1 t LBKHOZ t LBIXKH t LBIVKH t LBIVKH t LBKHOZ e2v semiconductors SAS 2010 t LBIXKH ...
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... Figure 10-6. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) GPCM Mode Output Signals: UPM Mode Input Signal: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] e2v semiconductors SAS 2010 LCLK LBKLOV LCS[0:7]/LWE LUPWAIT ...
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... LCS[0:3]/LWE t LUPWAIT t Input Signals: t LBKHOV1 Symbol Condition V – – – – LBKHOZ1 t LBIXKH2 LBIVKH2 t LBIXKH1 LBIVKH1 t LBKHOZ1 Min Max OV 0 0.3 – 0.3 0.8 – ±5 – 2.4 – 0.5 – 0.4 – e2v semiconductors SAS 2010 Unit V V µ ...
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... TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. e2v semiconductors SAS 2010 provides the JTAG AC timing specifications as defined in 41.. (1) Table 2-2 on page ...
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... Data Outputs 40 1037A–HIREL–06/ 50Ω Output 0 JTAG JTKHKL t JTG VM = Midpoint Voltage ( TRST VM = Midpoint Voltage ( JTKLDV t JTKLDX t JTKLDZ Output Data Valid VM = Midpoint Voltage ( 50Ω JTGR t JTGF JTDVKH t JTDXKH Input Data Valid Output Data Valid e2v semiconductors SAS 2010 ...
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... Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF. 3. Refer to the PC8349/E Integrated Host Processor Family Reference Manual, for information on the dig- ital filter used. 4. I/O pins obstruct the SDA and SCL lines if OV e2v semiconductors SAS 2010 VM t JTKLOV t ...
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... I2C 2 symbolizes I C timing (I2) for the I2PVKH clock reference (K) I2C (min) of the SCL signal) to bridge the the SCL signal. I2CL AC parameter. I2CF 50Ω L e2v semiconductors SAS 2010 Unit kHz µs µs µs µs ns µs ns µs µ for inputs and t (first ...
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... DC electrical characteristics for the PCI interface of the PC8349/E. Table 13-1. PCI DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage Input current High-level output voltage Low-level output voltage Note: 1. The symbol V e2v semiconductors SAS 2010 2 C bus I2DVKH I2KHKL t I2SXKL t t ...
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... Max Unit 11 ns – ns – – ns – ns – clocks – (first two letters of functional block)(signal)(state)(refer- for outputs. For example, t e2v semiconductors SAS 2010 Notes (3) (3) (3)(4) (3)(5) (3)(5) (6) (6) PCIVKH PCRHFV Notes (2) (2) (2)(3) (2)(4) (2)(4) (5) (5) PCIVKH ...
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... Figure 13-1. PCI AC Test Load Figure 13-2 shows the PCI input AC timing diagram. Figure 13-2. PCI Input AC Timing Diagram Figure 13-3 shows the PCI output AC timing diagram. Figure 13-3. PCI Output AC Timing Diagram e2v semiconductors SAS 2010 Output Z = 50Ω 0 CLK t ...
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... Min Max Unit 2.0 OV +0.3 DD –0.3 0.8 ±5 – 2.4 – 0.5 – 0.4 – (2) Min Unit 20 ns TIWID Min Max Unit 2.0 OV +0.3 DD –0.3 0.8 ±5 – 2.4 – 0.5 – 0.4 – e2v semiconductors SAS 2010 V V µ µ ...
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... Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are mea- sured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least t proper operation in edge triggered mode. e2v semiconductors SAS 2010 (1) (2) Symbol t ...
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... NIKHOX t – 8 NEKHOV t 2 – NEKHOX t 4 – NIIVKH t 0 – NIIXKH t 4 – NEIVKH t 2 – NEIXKH (first two letters of functional block)(signal)(state)(refer- for outputs. For example 50Ω L e2v semiconductors SAS 2010 Unit V V µ Unit NIKHOX ...
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... The package parameters are provided in the following list. The package type × 35 mm, 672 tape ball grid array (TBGA). Package outline Interconnects Pitch Module height (typical) Solder balls Ball diameter (typical) e2v semiconductors SAS 2010 Figure 17-3 on page 49 represent the AC timings from t t NEIVKH t NEKHOX ...
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... Parallelism measurement must exclude any effect of mark on top surface of package. 50 1037A–HIREL–06/ Index AREA D Top View (33) 0.5 35X Bottom view 672X 0. 0. 0.2 35X 1 0.5 (33) 1.05 0.80 1.69 1.24 0.74 3 672X Section D 0.1 M e2v semiconductors SAS 2010 A 4 Seating plane 0.1 min 0.64 0.44 ...
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... PCI2_FRAME/GPIO2[1] PCI2_TRDY/GPIO2[2] PCI2_IRDY/GPIO2[3] PCI2_STOP/GPIO2[4] PCI2_DEVSEL/GPIO2[5] PCI2_SERR/PCI1_ACK64 e2v semiconductors SAS 2010 Package Pin Number B34 C33 G30, G32, G34, H31, H32, H33, H34, J29, J32, J33, L30, K31, K33, K34, L33, L34, P34, R29, R30, R33, R34, T31, T32, T33, U31, U34, V31, ...
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... I OV – DD I/O GV – DD I/O GV – DD I/O GV – DD I/O GV – – DD I/O GV – – – – – – – – – – DD (9) I/O – (9) I/O I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – – DD e2v semiconductors SAS 2010 ...
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... GTM1_TGATE3/GTM2_TGATE4 GPIO1[8]/DMA_DDONE2/GTM1_TOUT3 GPIO1[9]/DMA_DREQ3/GTM1_TIN4/ GTM2_TIN3 GPIO1[10]/DMA_DACK3/ GTM1_TGATE4/GTM2_TGATE3 GPIO1[11]/DMA_DDONE3/ GTM1_TOUT4/GTM2_TOUT3 USB Port 1 MPH1_D0_ENABLEN/DR_D0_ENABLEN MPH1_D1_SER_TXD/DR_D1_SER_TXD MPH1_D2_VMO_SE0/DR_D2_VMO_SE0 e2v semiconductors SAS 2010 Package Pin Number AN24, AL23, AP25, AN25 AK23, AP26, AL24, AM25 AN26 AK24 AP27 AL25 AJ24 AN27 AP28 AL26 AM27 ...
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... I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – – DD I/O OV – DD I/O OV – – DD I/O OV – DD I/O OV – – I/O OV – DD I/O OV – DD I/O OV – DD I/O OV – – DD1 e2v semiconductors SAS 2010 ...
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... TSEC2_TXD[7]/GPIO1[31] TSEC2_TXD[6]/ DR_XCVR_TERM_SEL TSEC2_TXD[5]/ DR_UTMI_OPMODE1 TSEC2_TXD[4]/ DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] TSEC2_TX_ER/GPIO1[24] TSEC2_TX_EN/GPIO1[12] TSEC2_TX_CLK/GPIO1[30] DUART UART_SOUT[1:2]/MSRCID[0:1]/ LSRCID[0:1] UART_SIN[1:2]/MSRCID[2:3]/ LSRCID[2:3] UART_CTS[1]/MSRCID4/LSRCID4 e2v semiconductors SAS 2010 Package Pin Number E9 C8 A17 F12 D10 A11 B11 B17 B16, D16, E16, F16 E10, A8, F10, B8 ...
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... A18 C18 B18 D18 K32 Pin Type Power Supply Notes I/O OV – – DD (2) I (2) I (2) I (2) I I/O OV – DD I/O OV – DD I/O OV – – – – – – – – – – – – DD (1) I (2) I (8) I e2v semiconductors SAS 2010 ...
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... GND DD1 LV DD2 V DD e2v semiconductors SAS 2010 Package Pin Number L31 AP12 AE1 AJ13 A1, A34, C1, C7, C10, C11, C15, C23, C25, C28, D1, D8, D20, D30, E7, E13, E15, E17, E18, E21, E23, E25, E32, F6, F19, F27, F30, F34, G31, H5, J4, J34, K30, L5, M2, M5, M30, ...
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... AG29, AJ17, AJ30, AK11, AL15, AL19, AL21, AL29, AL30, AM20, AM23, AM24, AM26, AM28, AN11, AN13 M3 AD2 Pin Type Power Supply Notes PCI, 10/100 Ethernet, and OV – DD other standard (3.3 V) DDR reference I – voltage DDR reference I – voltage . e2v semiconductors SAS 2010 ...
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... PCI agent devices in the system, to allow the PC8349/E to function. When the PC8349/E is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND. e2v semiconductors SAS 2010 e300 Core Core PLL csb_clk ...
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... Table 19-1 specifies which units have a configurable clock Default Frequency csb_clk/3 csb_clk/3 csb_clk/3 csb_clk/3 csb_clk Options Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk e2v semiconductors SAS 2010 ...
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... RCWL[LBIUCM]). 19.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. cation factor encodings for the system PLL. Table 19-3. System PLL Multiplication Factors e2v semiconductors SAS 2010 Table 2-2 on page 7). 400 MHz 266–400 100–266 (2) 100– ...
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... SAS 2010 (2) 66.67 133 100 200 133 266 166 333 200 233 266 300 333 133 100 200 133 266 ...
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... Low High High High High High High High Notes: 1. CFG_CLKIN_DIV doubles csb_clk if set high. 2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. e2v semiconductors SAS 2010 csb_clk : Input SPMF Clock Ratio (2) 0010 2:1 0011 3:1 0100 4:1 ...
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... Ratio VCO Divider 1:1 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1 e2v semiconductors SAS 2010 ( ...
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... The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and COREPLL settings given in the table. 2. The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. e2v semiconductors SAS 2010 400 MHz Device Input ...
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... R 11 °C/W ΘJMA R 8 °C/W ΘJMA R 9 °C/W ΘJMA R 7 °C/W ΘJMA R 3.8 °C/W ΘJB R 1.7 °C/W ΘJC Ψ 1 °C the power dissipation of the I/O drivers. I/O e2v semiconductors SAS 2010 Notes (1)(2) (1)(3) (1)(3) (1)(3) (1)(3) (1)(3) (4) (5) (6) ...
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... A small amount of epoxy is placed over the thermocouple junction and over about wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. e2v semiconductors SAS 2010 × ...
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... For instance, the user can change the size of ΘCA 35 × TBGA Air Flow Thermal Resistance Natural convection 1 m/s 2 m/s Natural convection 1 m/s 2 m/s Natural convection 1 m/s 2 m/s Natural convection 1 m/s 2 m/s 1 m/s e2v semiconductors SAS 2010 10 6.5 5.6 8.4 4.7 4 5.7 3.5 2.7 6.7 4.1 2.8 3.1 ...
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... Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com e2v semiconductors SAS 2010 PC8349/E [Preliminary] 603-224-9988 408-567-8082 408-436-8770 800-522-2800 603-635-5102 781-935-4850 800-248-2481 888-642-7674 1037A–HIREL–06/10 ...
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... PLL ratio configuration bits as described in 70 1037A–HIREL–06/10 × Section 19.1 ”System PLL Configuration” on page Section 19.2 ”Core PLL Configuration” on page 800-347-4572 61. 64. e2v semiconductors SAS 2010 ...
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... ESR (equivalent series resistance) rating to ensure the quick response time. They should also be connected to the power and ground planes through two vias to minimize inductance. Sug- gested bulk capacitors are 100-330 µF (AVX TPS tantalum or Sanyo OSCON). e2v semiconductors SAS 2010 , and preferably these voltages are derived directly from V DD pin being supplied ...
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... and GND pins C). /2 (see Figure 21-2). The DD is trimmed until the voltage at the pad P and R are designed SW2 Pad SW1 R P OGND . The measured voltage is V term = R × – 1). The drive source term 1 2 e2v semiconductors SAS 2010 ...
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... Target NA = 105 ° C. Table 2-1 on page ™ Design Checklist. ™ II Pro Integrated Host Processor Hardware Specifications (Document Order No. shows an analysis of the e2v part numbering nomenclature for the PC8349/E. PC8349/E [Preliminary] (Including DDR DRAM 42 Target 20 Target 42 Target 20 Target NA NA 1037A–HIREL–06/10 ...
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... For availability of the different versions, contact your local e2v sales office. 5. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX part- number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes ...
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... Three-Speed Ethernet Controller (TSEC) – GMII/MII/TBI/RGMII/RTBI 8.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications ................................. 22 8.3 Ethernet Management Interface Electrical Characteristics ................................... 29 9 USB ......................................................................................................... 31 9.1 USB DC Electrical Characteristics ........................................................................ 31 9.2 USB AC Electrical Specifications .......................................................................... 31 e2v semiconductors SAS 2010 Electrical Characteristics ................................................................................. 20 PC8349/E [Preliminary] 1037A–HIREL–06/10 i ...
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... Package and Pin Listings ..................................................................... 49 18.1 Package Parameters for the PC8349/E TBGA ................................................... 49 18.2 Mechanical Dimensions for the PC8349/E TBGA ............................................... 50 18.3 Pinout Listings ..................................................................................................... 51 19 Clocking .................................................................................................. 59 19.1 System PLL Configuration ................................................................................... 61 19.2 Core PLL Configuration ....................................................................................... 64 19.3 Suggested PLL Configurations ............................................................................ 65 ii 1037A–HIREL–06/10 e2v semiconductors SAS 2010 ...
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... Output Buffer DC Impedance .............................................................................. 72 21.6 Configuration Pin Multiplexing ............................................................................. 73 21.7 Pull-Up Resistor Requirements ........................................................................... 73 22 Ordering Information ............................................................................. 73 22.1 Part Numbers Fully Addressed by This Document ............................................. 73 23 Definitions .............................................................................................. 74 23.1 Life Support Applications ..................................................................................... 74 24 Document Revision History .................................................................. 74 e2v semiconductors SAS 2010 PC8349/E [Preliminary] 1037A–HIREL–06/10 iii ...
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... Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein ...