IDT74FCT162H272ATPV8 IDT, Integrated Device Technology Inc, IDT74FCT162H272ATPV8 Datasheet - Page 3

• Manufacturer Part Number: IDT74FCT162H272ATPV8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74FCT162H272ATPV8

• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTION
FUNCTION TABLES
NOTES:
1. Output level before the indicated steady-state input conditions were established.
2. H = HIGH Voltage Level
NOTE:
1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
IDT74FCT162H272AT/CT
FAST CMOS 12-BIT SYNCHRONOUS BUS EXCHANGER
1B
H
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
X
X
X
X
X
CEA1B
CEA2B
L
Signal
1B
2B
CE1B
CE2B
A
OEA
OEB
CLK
SEL
(1:12)
H
H
H
A
L
L
L
X
X
X
(1:12)
(1:12)
2B
H
X
X
X
X
X
L
CEA1B
H
H
H
X
X
L
L
L
L
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
SEL
H
H
H
X
L
L
L
CEA2B
Inputs
H
H
H
X
X
L
L
L
L
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
Clock Input
Clock Enable Input for the A-1B Register. If CEA1B is LOW during the rising edge of CLK, data will be clocked into register A-1B
(Active LOW).
Clock Enable Input for the A-2B Register. If CEA2B is LOW during the rising edge of CLK, data will be clocked into register A-2B
(Active LOW).
Clock Enable Input for the 1B-A Register. If CE1B is LOW during the rising edge of CLK, data will be clocked into register 1B-A
(Active LOW).
Clock Enable Input for the 2B-A Register. If CE2B is LOW during the rising edge of CLK, data will be clocked into register 2B-A
(Active LOW).
1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to A Port. When LOW during
the rising edge of CLK, SEL enables data transfer from 2B Port to A Port.
Synchronous Output Enable for A Port (Active LOW).
Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
Inputs
CE1B
H
X
X
X
X
L
L
OEB
CE2B
H
L
L
L
L
L
L
L
L
(2)
H
X
X
X
X
L
L
CLK
OEA
↑
↑
↑
↑
↑
↑
↑
↑
↑
H
L
L
L
L
L
L
Active
CLK
B
B
B
↑
↑
↑
↑
↑
↑
↑
1B
H
H
L
L
Z
(1)
(1)
(1)
Outputs
Output
Active
A
A
H
H
A
L
L
Z
B
B
B
(1)
(1)
2B
H
H
L
L
Z
(1)
(1)
(1)
Description
3
(1)
(1)
(1)
INDUSTRIAL TEMPERATURE RANGE