MC145484SD Freescale, MC145484SD Datasheet - Page 4

• Manufacturer Part Number: MC145484SD
• Manufacturer: Freescale
• Type: PCMr

Specifications of MC145484SD

• Number Of Channels: 1
• Gain Control: Adjustable
• Number Of Adc's: 1
• Number Of Dac's: 1
• Adc/dac Resolution: 13b
• Package Type: SSOP
• Sample Rate: 8KSPS
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 20
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

RO–
Receive Analog Output (Inverting) (Pin 2)
from the digital–to–analog converter. This output is capable
of driving a 2 k load to 1.575 V peak referenced to the V AG
pin. If the device is operated half–channel with the FST pin
clocking and FSR pin held low, the receive filter input will be
conencted to the V AG voltage. This minimizes transients at
the RO– pin when full–channel operation is resumed by
clocking the FSR pin. This pin is high impedance when the
device is in the powered–down mode.
PI
Power Amplifier Input (Pin 3)
inverting input to the PO– amplifier is internally tied to the
V AG pin. The PI and PO– pins are used with external resis-
tors in an inverting op amp gain circuit to set the gain of the
PO+ and PO– push–pull power amplifier outputs. Connect-
ing PI to V DD will power down the power driver amplifiers and
the PO+ and PO– outputs will be high impedance.
PO–
Power Amplifier Output (Inverting) (Pin 4)
to provide a feedback signal to the PI pin to set the gain of
the push–pull power amplifier outputs. This pin is capable of
driving a 300
differential (push–pull) and capable of driving a 300
3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage
and signal reference of this output is the V AG pin. The V AG
pin cannot source or sink as much current as this pin, and
therefore low impedance loads must be between PO+ and
PO–. The PO+ and PO– differential drivers are also capable
of driving a 100
transducer in series with a 20
in distortion. These drivers may be used to drive resistive
loads of
Connecting PI to V DD will power down the power driver am-
plifiers and the PO+ and PO– outputs will be high imped-
ance. This pin is also high impedance when the device is
powered down by the PDI pin.
PO+
Power Amplifier Output (Non–Inverting) (Pin 5)
an inverted version of the signal at PO–. This pin is capable
of driving a 300
power down the power driver amplifiers and the PO+ and
PO– outputs will be high impedance. This pin is also high im-
pedance when the device is powered down by the PDI pin.
See PI and PO– for more information.
DIGITAL INTERFACE
MCLK
Master Clock (Pin 11)
to this pin is used to generate the internal 256 kHz clock and
sequencing signals for the switched–capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on
MC145484
4
This is the inverting output of the receive smoothing filter
This is the inverting input to the PO– amplifier. The non–
This is the inverting power amplifier output, which is used
This is the non–inverting power amplifier output, which is
This is the master clock input pin. The clock signal applied
32
load to PO+. The PO+ and PO– outputs are
when the gain of PO– is set to 1/4 or less.
load to PO–. Connecting PI to V DD will
resistive load or a 100 nF Piezoelectric
resister with a small increase
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
load to
this pin to the clock at FST (8 kHz) and will automatically
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For
MCLK frequencies of 256 and 512 kHz, MCLK must be syn-
chronous and approximately rising edge aligned to FST. For
optimum performance at frequencies of 1.536 MHz and
higher, MCLK should be synchronous and approximately ris-
ing edge aligned to the rising edge of FST. In many ap-
plications, MCLK may be tied to the BCLKT pin.
FST
Frame Sync, Transmit (Pin 14)
put of the serial PCM data at the DT pin. This input is com-
patible with various standards including IDL, Long Frame
Sync, Short Frame Sync, and GCI formats. If both FST and
FSR are held low for several 8 kHz frames, the device will
power down.
BCLKT
Bit Clock, Transmit (Pin 12)
the IDL and GCI modes it also controls the transfer rate of
the receive PCM data. This pin can accept any bit clock fre-
quency from 64 to 4096 kHz for Long Frame Sync and Short
Frame Sync timing. This pin can accept clock frequencies
from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz
to 6.176 MHz for GCI timing mode.
DT
Data, Transmit (Pin 13)
pedance except when outputting PCM data. When operating
in the IDL or GCI mode, data is output in either the B1 or B2
channel as selected by FSR. This pin is high impedance
when the device is in the powered down mode.
FSR
Frame Sync, Receive (Pin 7)
mode, this pin accepts an 8 kHz clock, which synchronizes
the input of the serial PCM data at the DR pin. FSR can be
asynchronous to FST in the Long Frame Sync or Short
Frame Sync modes. When an ISDN mode (IDL or GCI) has
been selected with BCLKR, this pin selects either B1 (logic 0)
or B2 (logic 1) as the active data channel.
BCLKR
Bit Clock, Receive (Pin 9)
mode, this pin accepts any bit clock frequency from 64 to
4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,
and DR become IDL Interface compatible. When this pin is
held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-
face compatible.
DR
Data, Receive (Pin 8)
Sync or Short Frame Sync mode is controlled by FSR and
BCLKR. When in the IDL or GCI mode, this data transfer is
controlled by FST and BCLKT. FSR and BCLKR select the
B channel and ISDN mode, respectively.
This pin accepts an 8 kHz clock that synchronizes the out-
This pin controls the transfer rate of transmit PCM data. In
This pin is controlled by FST and BCLKT and is high im-
When used in the Long Frame Sync or Short Frame Sync
When used in the Long Frame Sync or Short Frame Sync
This pin is the PCM data input, and when in a Long Frame
MOTOROLA