MC145483DW Freescale, MC145483DW Datasheet - Page 14

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MC145483DW

Manufacturer Part Number
MC145483DW
Description
Manufacturer
Freescale
Type
PCMr
Datasheet

Specifications of MC145483DW

Number Of Channels
1
Gain Control
Adjustable
Number Of Adc's
1
Number Of Dac's
1
Adc/dac Resolution
13b
Package Type
SOIC W
Sample Rate
8KSPS
Number Of Adc Inputs
1
Number Of Dac Outputs
1
Operating Supply Voltage (min)
2.7V
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
20
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC145483DW
Manufacturer:
INTEL
Quantity:
700
Part Number:
MC145483DW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(V DD = 2.7 to 3.6 V, V SS = 0 V, All Digital Signals Referenced to V SS , T A = – 40 to + 85°C, C L = 150 pF, Unless Otherwise Noted)
Ref.
No.
10
12
13
14
15
16
17
18
19
20
21
22
23
11
1
1
2
3
4
5
6
7
8
9
Master Clock Frequency for MCLK
MCLK Duty Cycle for 256 kHz Operation
Minimum Pulse Width High for MCLK (Frequencies of 512 kHz or Greater)
Minimum Pulse Width Low for MCLK (Frequencies of 512 kHz or Greater)
Rise Time for All Digital Signals
Fall Time for All Digital Signals
Setup Time from MCLK Low to FST High
Setup Time from FST High to MCLK Low
Bit Clock Data Rate for BCLKT or BCLKR
Minimum Pulse Width High for BCLKT or BCLKR
Minimum Pulse Width Low for BCLKT or BCLKR
Hold Time from BCLKT (BCLKR) Low to FST (FSR) High
Setup Time for FST (FSR) High to BCLKT (BCLKR) Low
Setup Time from DR Valid to BCLKR Low
Hold Time from BCLKR Low to DR Invalid
Hold Time from 2nd Period of BCLKT (BCLKR) Low to FST (FSR) Low
Delay Time from FST or BCLKT, Whichever is Later, to DT for Valid MSB Data
Delay Time from BCLKT High to DT for Valid Data
Delay Time from the Later of the 13th (16th for Sign–Extended Mode) BCLKT
Falling Edge, or the Falling Edge of FST to DT Output High Impedance
Minimum Pulse Width Low for FST or FSR
Hold Time from BCLKT (BCLKR) Low to FST (FSR) Low
Setup Time from FST (FSR) Low to MSB Period of BCLKT (BCLKR) Low
Delay Time from BCLKT High to DT Data Valid
Delay Time from the 13th (16th for Sign–Extended Mode) BCLKT Low to DT
Output High Impedance
Freescale Semiconductor, Inc.
For More Information On This Product,
Characteristics
Go to: www.freescale.com
SHORT FRAME SPECIFIC TIMING
LONG FRAME SPECIFIC TIMING
Min
256
45
50
50
50
50
50
50
20
80
50
50
10
50
50
50
10
10
0
1536
1544
2048
2560
4096
Typ
256
512
4096
Max
55
50
50
60
60
60
60
60
Unit
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%

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