ICS9FG104DFLFT IDT, Integrated Device Technology Inc, ICS9FG104DFLFT Datasheet - Page 11

• Manufacturer Part Number: ICS9FG104DFLFT
• Description: IC FREQ TIMING GENERATOR 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG104DFLFT

• Input: Clock, Crystal
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 150mA
• Pll Input Freq (min): 12.886MHz
• Pll Input Freq (max): 27.5MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SSOP
• Output Frequency Range: 100 to 400MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1254-2; 9FG104DFLFT

IDT
SMBus Table: PLL Frequency Control Register
SMBus Table: PLL Spread Spectrum Control Register
SMBus Table: PLL Spread Spectrum Control Register
Byte 11
Byte 12
Byte 13
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
®
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin #
Pin #
Pin #
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PLL N Div7
PLL N Div6
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
PLL N Div1
PLL N Div0
PLL SSP14
PLL SSP13
PLL SSP12
PLL SSP11
PLL SSP10
PLL SSP7
PLL SSP6
PLL SSP5
PLL SSP4
PLL SSP3
PLL SSP2
PLL SSP1
PLL SSP0
PLL SSP9
PLL SSP8
Name
Name
Name
Byte11 bit(7:0) and Byte10
N Divider Programming
Programming bit(14:8)
Programming bit(7:0)
Control Function
Control Function
Control Function
Spread Spectrum
Spread Spectrum
bit(7:6)
Reserved
11
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
and N Divider in Byte 11 and 12 will
Byte 0 Rom table. VCO Frequency
configure the PLL VCO frequency.
The decimal representation of M
Default at power up = latch-in or
Byte 13 and 14 will program the
Byte 13 and 14 will program the
These Spread Spectrum bits in
These Spread Spectrum bits in
= fXTAL x [NDiv(9:0)+8] /
spread pecentage of PLL
spread pecentage of PLL
0
0
0
[MDiv(5:0)+2]
1
1
1
Default
Default
Default
1541C—12/16/10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0