MAX3634ETM+ Maxim Integrated Products, MAX3634ETM+ Datasheet - Page 4

• Manufacturer Part Number: MAX3634ETM+
• Description: IC CLOCK PHASE ALIGNER 48-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Clock Phase Alignerr

Specifications of MAX3634ETM+

• Input: LVPECL
• Output: LVPECL
• Frequency - Max: 155MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Frequency-max: 155MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
4
(V
1, 2, 12, 25, 36, 37, 48
21, 24, 26, 29, 32, 35
CC
11, 38, 39, 44, 47
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
_______________________________________________________________________________________
0
13–20, 22, 23
= +3.3V and T
3, 6, 7, 10
0
JITTER TOLERANCE vs. SDI-TO-REFCLK
41, 43
PIN
EP
27
28
30
31
33
34
40
42
45
46
4
5
8
9
200
SDI-TO-REFCLK PHASE (ps)
LIMITED BY TEST EQUIPMENT
PHASE (1.244Gbps)
A
= +25°C, unless otherwise noted)
400
Exposed Pad The exposed pad must be connected to the ground plane for proper thermal performance.
REFCLK+
RATESEL
REFCLK-
LOCK+
SCLK+
LOCK-
NAME
SCLK-
SDO+
V
RST+
V
TEST
SDO-
GND
V
SDI+
RST-
SDI-
V
FILT
CC
CC
CC
600
CC
O
V
I
800
Supply Ground
+3.3V Supply for Input Buffers
Positive Serial Data Input, LVPECL
Negative Serial Data Input, LVPECL
Positive Reset Input, LVPECL. Reset (= RST+ - RST-) is falling edge triggered.
Negative Reset Input, LVPECL
+3.3V Supply for Digital Circuitry
Production Test Pins, Reserved. Leave open for normal operation.
+3.3V Supply for Output Buffers
Negative Lock Status Output, LVPECL
Positive Lock Status Output, LVPECL. Lock (= (LOCK+) - (LOCK-)) high indicates that the
MAX3634 has acquired the correct phase.
Negative Serial Data Output, LVPECL
Positive Serial Data Output, LVPECL
Negative Serial Clock Output, LVPECL
Positive Serial Clock Output, LVPECL
Rate Select Input, TTL. High selects 622.08Mbps operation.
+3.3V Supply for VCO
PLL Filter Capacitor. Connect a 0.1µF X7R capacitor from pin 42 to V
Negative Reference Clock Input, LVPECL (1/8th data rate)
Positive Reference Clock Input, LVPECL
Typical Operating Characteristics (continued)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
JITTER TOLERANCE vs. SDI-TO-REFCLK
LIMITED BY TEST EQUIPMENT
200
SDI-TO-REFCLK PHASE (ps)
PHASE (622Mbps)
400
600
FUNCTION
800
340
320
300
280
260
240
220
200
-50
EXCLUDES PECL OUTPUT CURRENT
AMBIENT TEMPERATURE (°C)
Pin Description
vs. TEMPERATURE
SUPPLY CURRENT
0
CC
V.
50
100