IDTCV110NPAG IDT, Integrated Device Technology Inc, IDTCV110NPAG Datasheet - Page 10

• Manufacturer Part Number: IDTCV110NPAG
• Description: IC FLEXPC CLK PROGR P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV110NPAG

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV110NPAG

Byte 18, bit[2:0] controls PCIF[2:0] strength.
Byte 26, bit[2:0] controls PCI[5:0] strength.
Byte 27, Byte 28 controls the magnitude of the SRC spread.
Byte 30, Byte 31 sets the center of the frequency of the SRC.
Byte 23, bit[3:0] controls the CPU PLL spread.
NOTE:
1. Write byte 9 prior to Bytes 27, 28, 30, and 31.
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
APPLICATION NOTE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
IDTCV110N
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
Symbol
I
I
V
V
DD3.3OP
DD3.3PD
T
C
C
IH
IL
L
C
V
STAB
V
I
OUT
F
PIN
INX
_FS
_FS
IL
IH
IN
IL
I
Bits
111
011
001
000
Input HIGH Voltage
Input LOW Voltage
LOW Voltage, HIGH Threshold
LOW Voltage, LOW Threshold
Input LeakageCurrent
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clock Stabilization
Modulation Frequency
T
T
T
DRIVE
FALL
RISE
_PD
_PD
_PD
A
(3)
(2)
(2)
= 0°C to +70°C, Supply Voltage: V
Parameter
(2)
(1)
(2)
(2,3)
(2)
3.3V ± 5%
3.3V ± 5%
For FSA.B.C test_mode
0< V
Full active, C
All differential pairs driven
All differential pairs tri-stated
V
Logic inputs
Output pin capacitance
X1 and X2 pins
From V
Triangular modulation
CPU output enable after PD de-assertion
Fall time of PD
Rise time of PD
Strength
For FSA.B.C test_mode
DD
0.6x
0.8x
1.2x
1x
IN
= 3.3V
< V
DD
DD
(1)
DD
power-up or de-assertion of PD to first clock
(1)
, no internal pull-up or pull-down
= 3.3V ± 5%
L
= full load
Test Conditions
10
COMMERCIAL TEMPERATURE RANGE
V
V
SS
SS
Min.
0.7
–5
—
—
—
—
—
—
—
—
—
30
—
—
—
2
- 0.3
- 0.3
14.31818
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
V
DD
DD
Max.
0.35
400
300
0.8
1.8
+5
70
12
—
33
7
5
6
5
5
5
+ 0.3
+ 0.3
MHz
KHz
Unit
mA
mA
mA
nH
ms
pF
us
ns
ns
V
V
V
V