ICS94228BF IDT, Integrated Device Technology Inc, ICS94228BF Datasheet - Page 5

• Manufacturer Part Number: ICS94228BF
• Description: IC CLOCK CHIP PROGR AMDK7 48SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS94228BF

• Input: Crystal
• Output: Clock
• Frequency - Max: 233.33MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 233.33MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 94228BF

Third party brands and names are the property of their respective owners.
Notes:
1.
2.
3.
4.
5.
6.
7.
The ICS clock generator is a slave/receiver, I
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Functionality & Frequency
Select Register
Output Control Registers
Vendor ID & Revision ID
Registers
Byte Count
Read Back Register
Watchdog Enable Register
Watchdog Control Registers
VCO Control Selection Bit
VCO Frequency Control
Registers
Spread Spectrum Control
Registers
Group Skews Control
Registers
Output Rise/Fall Time
Select Registers
Programmable System Frequency Generator
Register Name
Brief I
2
C registers description for ICS94228
2
C interface, the protocol is set to use only Block-Writes from the controller. The
1, 2, 3
5, 6, 7
11, 12
13, 14
15, 16
9, 10
Byte
4, 5
0
8
4
2
C component. It can read back the data stored in the latches for
Output frequency, hardware / I
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
These registers control the spread
percentage amount.
Increment or decrement the group skew
amount as compared to the initial skew.
These registers will control the output
rise and fall time.
5
Description
Preliminary Product Preview
H
to this byte.
2
C
PWD Default
See individual
byte description
See individual
byte description
See individual
byte description
Depended on
hardware/byte 0
configuration
Depended on
hardware/byte 0
configuration
See individual
byte description
See individual
byte description
000,0000
08
10
0
H
H
ICS94228