SI5368C-C-GQR Silicon Laboratories Inc, SI5368C-C-GQR Datasheet
SI5368C-C-GQR
Specifications of SI5368C-C-GQR
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SI5368C-C-GQR Summary of contents
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Description The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from ...
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Si5368 2 Preliminary Rev. 0.41 ...
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T C ABLE O F ONTENTS Section 1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5368 Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T Supply Voltage V Supply Current I DD (Supply current is independent Input Clock ...
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Table 1. Performance Specifications (Continued 1.8 ±5%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Input Voltage Level Limits CKN Common Mode Voltage CKN Rise/Fall Time CKN Duty Cycle CKN (Minimum Pulse Width) Output Clocks ...
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Si5368 Table 1. Performance Specifications (Continued 1.8 ±5%, 2.5 V ±10%, or 3.3 V ±10 Parameter Symbol Package Thermal Resistance Junction to Ambient Notes: 1. For a more comprehensive listing of device specifications, please consult ...
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MHz in, 622.08 MHz out 0 -20 -40 -60 -80 -100 -120 -140 -160 100 1000 10000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot Jitter Band Brick Wall, 100 Hz to 100 MHz SONET_OC48, 12 kHz to ...
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Si5368 System Power Supply 130 130 82 82 Input Clock V = 3.3 V Sources* DD 130 130 82 82 INC DEC Rate Control Mode (L) Reset ...
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Functional Description The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from ...
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Si5368 2. Pin Descriptions: Si5368 100 RST NC 4 VDD 5 6 VDD GND 7 GND 8 C1B 9 10 C2B C3B 11 12 INT_ALM CS0_C3A 13 GND 14 15 VDD XA 16 ...
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Table 3. Si5368 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 5, 6, 15, 27, V Vdd DD 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 7, 8, 14, 18, GND GND 19, ...
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Si5368 Table 3. Si5368 Pin Descriptions (Continued) Pin # Pin Name I/O 13 CS0_C3A I/O 57 CS1_C4A FS_ALIGN I 29 CKIN4 CKIN4– 32 RATE0 I 42 RATE1 Note: Internal register names are ...
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Table 3. Si5368 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 34 CKIN2 CKIN2– 39 CKIN3 CKIN3– 44 CKIN1 CKIN1– 49 LOL O 54 DEC I Note: Internal register names are indicated ...
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Si5368 Table 3. Si5368 Pin Descriptions (Continued) Pin # Pin Name I/O 55 INC I 58 C1A O 59 C2A O 60 SCL I 61 SDA_SDO I A2_SS I Note: Internal register names are ...
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Table 3. Si5368 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 71 SDI I 77 CKOUT3 CKOUT3– 82 CKOUT1– CKOUT1+ 87 FS_OUT– FS_OUT+ 90 CMODE I 92 CKOUT2 CKOUT2– 97 ...
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Si5368 3. Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined ...
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Register N1_HS [2: N2_HS [2: ...
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Si5368 Register 128 129 130 CLAT- DIGHOLD- PROGRESS VALID 131 132 ALIGN_FLG 133 134 135 PARTNUM_RO [3:0] 136 RST_REG ICAL 138 139 LOS4_EN LOS3_EN [0:0] [0:0] 140 141 142 143 144 185 ...
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Register Descriptions Register 0. Bit D7 D6 Name FREE_ RUN Type R R/W Reset value = 0001 0100 Bit Name 7 Reserved Reserved. 6 FREE_RUN Free Run. Internal to the device, route XA/XB to CKIN2. This allows the device ...
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Si5368 Register 1. Bit D7 D6 Name CK_PRIOR4 [1:0] Type R/W R/W Reset value = 1110 0100 Bit Name 7:6 CK_PRIOR4 Selects which of the input clocks will be 4th priority in the autoselection state machine. [1:0] 00: CKIN0 is ...
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Register 2. Bit D7 D6 Name BWSEL_REG [3:0] Type R/W Reset value = 0100 0010 Bit Name 7:4 BWSEL_REG BWSEL_REG. [3:0] Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After BWSEL_REG is written with a new value, ...
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Si5368 4 SQ_ICAL SQ_ICAL. This bit determines if the output clocks will remain enabled or be squelched (disabled) during an internal calibration. See Table 4. 0: Output clocks enabled during ICAL. 1: Output clocks disabled during ICAL. 3:0 Reserved Reserved. ...
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Bit Name 7:6 ICMOS [1:0] ICMOS [1:0]. When the output buffer is set to CMOS mode, these bits determine the output buffer drive strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation. These ...
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Si5368 Register 6. Bit D7 D6 Name Reserved SLEEP Type R R/W Reset value = 0010 1100 Bit Name 7 Reserved Reserved. 6 SLEEP SLEEP. In sleep mode, the clock outputs are disabled and the maximum amount of internal circuitry ...
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SFOUT3_ SFOUT3_REG [2:0]. REG [2:0] Controls output signal format and disable for CKOUT3 output buffer. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format pin ...
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Si5368 5:3 SFOUT5_ SFOUT5_REG [2:0] REG [2:0] Controls output signal format and disable for CKOUT5 output buffer. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in the allowed output format ...
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HLOG_3 [1:0] HLOG_3 [1:0]. 00: Normal operation 01: Holds CKOUT3 output at static logic 0. Entrance and exit from this state will occur without glitches or runt pulses. 10: Holds CKOUT3 output at static logic 1. Entrance and exit ...
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Si5368 Register 10. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5 DSBL5_ DSBL5_REG. REG This bit controls the powerdown and disable of the CKOUT5 output buffer. If disable mode is ...
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Register 11. Bit D7 D6 Name ALIGN_THR [2:0] Type R/W R/W Reset value = 0100 0000 Bit Name 7:5 ALIGN_THR ALIGN_THR [2:0]. [2:0] These bits control the threshold for the alignment error alarm. Input to output sync phase skews that ...
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Si5368 Register 12. Bit D7 D6 Name FPW_ FSYNC_ VALID ALIGN_ REG Type Reset value = 1000 1000 Bit Name 7 FPW_VALID FPW_VALID. When in frame sync mode (CK_CONFIG_REG=1), before writing either a new FSYNC_PW[9:0] or NC5_LS [19:0] value, this ...
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FSYNC_ FSYNC_SKEW [16:0]. SKEW [16:0] Phase skew control for FSYNCOUT. The resolution of the skew control is 1/fCKOUT2. Entered values should be less than the FSYNCOUT period. 0 0000 0000 0000 0000=Zero phase skew. 0 0000 0000 0000 0001=Delay ...
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Si5368 Register 15. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 FSYNC_ FSYNC_SKEW [7:0]. SKEW [7:0] See Register 12. Register 16. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 CLAT ...
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Register 17. Bit D7 D6 Name FLAT_ VALID Type R/W Reset value = 1000 0000 Bit Name 7 FLAT_VAILD FLAT_VAILD. Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the existing FLAT[14:0] value to ...
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Si5368 Register 19. Bit D7 D6 Name FOS_EN FOS_THR [1:0] Type R/W R/W Reset value = 0010 1100 Bit Name 7 FOS_EN FOS_EN. Frequency offset enable globally disables FOS. See the individual FOS enables (FOSx_EN, register 139). 00: FOS disable ...
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Register 20. Bit D7 D6 Name Reserved Type R Reset value = 0011 1100 Bit Name 7:6 Reserved Reserved. 5 ALRMOUT_ ALRMOUT_PIN. PIN The ALRMOUT status can be reflected on the ALRMOUT output pin. The request to reflect the interrupt ...
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Si5368 Register 21. Bit D7 D6 Name INCDEC_ Reserved PIN ALIGN_PIN Type R/W Force 1 Reset value = 1111 1111 Bit Name 7 INCDEC_PIN INCDEC_PIN. Determines how coarse skew adjustments can be made. The adjustments can be made via hardware ...
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CK1_ACTV_ CK1_ACTV_PIN. PIN The CK1_ACTV_REG status bit can be reflected to the CK1_ACTV output pin using the CK1_ACTV_PIN enable function. 0: CK1_ACTV output pin tristated. 1: CK1_ACTV status reflected to output pin. 0 CKSEL_PIN CKSEL_PIN. If manual clock selection ...
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Si5368 2 CK_BAD_ CK_BAD_POL. POL Sets the active polarity for the C1B, C2B, C3B, and ALRMOUT signals when reflected on output pins. 0: Active low 1: Active high 1 LOL_POL LOL_POL. Sets the active polarity for the LOL status when ...
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LOS1_MSK LOS1_MSK. Determines if a LOS on CKIN1 (LOS1_FLG) is used in the generation of an interrupt. Writes to this register do not change the value held in the LOS1_FLG register. 0: LOS1 alarm triggers active interrupt on INT ...
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Si5368 1 FOS1_MSK FOS1_MSK. Determines if the FOS1_FLG is used in the generation of an interrupt. Writes to this reg- ister do not change the value held in the FOS1_FLG register. 0: FOS1 alarm triggers active interrupt on INT output ...
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Register 26. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC1_LS NC1_LS [15:8]. [15:8] See Register 25. Register 27. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC1_LS [7:0] NC1_LS ...
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Si5368 Register 28. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3:0 NC1_LS NC2_LS [19:16]. [19:0] Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. ...
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Register 30. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC2_LS [7:0] NC2_LS [7:0]. See Register 28. Register 31. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:4 Reserved ...
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Si5368 Register 32. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC3_LS NC3_LS [15:8]. [15:8] See Register 31. Register 33. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC3_LS [7:0] ...
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Register 34. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3:0 NC4_LS NC4_LS [19:0]. [19:0] Sets value for NC4 low-speed divider, which drives CKOUT4 output. Must odd. 00000000000000000000=1 ...
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Si5368 Register 36. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC4_LS [7:0] NC4_LS [7:0]. See Register 34. Register 37. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:4 ...
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Register 38. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC5_LS NC5_LS [15:8]. [15:8] See Register 37. Register 39. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC5_LS [7:0] NC5_LS ...
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Si5368 Register 40. Bit D7 D6 Name N2_HS [2:0] Type R/W Reset value = 1100 0000 Bit Name 7:5 N2_HS [2:0] N2_HS [2:0]. Sets value for N2 high speed divider which drives NCn_LS ( low-speed divider. ...
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Register 42. Bit D7 D6 Name Type Reset value = 1111 1001 Bit Name 7:0 N2_LS [7:0] N2_LS [7:0]. See Register 40. Register 43. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:3 Reserved Reserved. 2:0 ...
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Si5368 Register 44. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N31 [15:8] N31 [15:8]. See Register 43. Register 45. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N31 [7:0] ...
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Register 46. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:3 Reserved Reserved. 2:0 N32_[18:0] N32_[18:0]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 ...
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Si5368 Register 48. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N32_[7:0] N32_[7:0]. See Register 46. Register 49. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 18:0 N33_[18:0] N33_[18:0]. Sets value ...
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Register 50. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N33_[15:8] N33_[15:8]. See Register 49. Register 51. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N33_[7:0] N33_[7:0]. See Register 49. ...
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Si5368 Register 52. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N34_[18:0] N34_[18:0]. Sets value for input divider for CKIN4. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider ...
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Register 54. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N34_[15:8] N34_[7:0]. See Register 52. Register 55. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5:3 ...
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Si5368 Register 56. Bit D7 D6 Name Reserved Type R Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5:3 CLKIN4RATE CLKIN4RATE[2:0]. [2:0] CKINn frequency selection for FOS alarm monitoring. 000 MHz 001 ...
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Register 128. Bit D7 D6 Name Reserved Type R Reset value = 0010 0000 Bit Name 7:4 Reserved Reserved. 3 CK4_ACTV_ CK4_ACTV_REG. REG Indicates if CKIN4 is currently the active clock for the PLL input. 0: CKIN4 is not the ...
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Si5368 Register 129. Bit D7 D6 Name Reserved Type R Reset value = 0001 1110 Bit Name 7:5 Reserved Reserved. 4 LOS4_INT LOS4_INT. Indicates the LOS status on CKIN4. 0: Normal operation. 1: Internal loss-of-signal alarm on CKIN4 input. 3 ...
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Register 130. Bit D7 D6 Name CLAT- DIGHOLD- PROGRESS VALID Type R R Reset value = 0000 0001 Bit Name 7 CLAT- CLAT Progress. PROGRESS Indicates if the last change in the CLAT register has been processed. 0: Coarse skew ...
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Si5368 Register 131. Bit D7 D6 Name Reserved Type R Reset value = 0001 1111 Bit Name 7:5 Reserved Reserved. 4 LOS4_FLG LOS4_FLG. CKIN4 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS4_INT. Generates active output interrupt if output ...
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Register 132. Bit D7 D6 Name Reserved ALIGN_ FOS4_FLG FOS3_FLG FOS2_FLG FOS1_FLG FLG Type R R/W Reset value = 0000 0010 Bit Name 7 Reserved Reserved. 6 ALIGN_FLG ALIGN_FLG. Alignment Alarm Flag. 0: Normal operation. 1: Held version of ALIGN_INT. ...
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Si5368 1 LOL_FLG LOL_FLG. PLL Loss of Lock Flag. 0: PLL locked 1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by ...
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Register 134. Bit D7 D6 Name Type Reset value = 0000 0100 Bit Name 7:0 PARTNUM_ PARTNUM_RO [11:0]. RO [11:0] Device ID: 0000 0100 0100'b=Si5368 Register 135. Bit D7 D6 Name PARTNUM_RO [3:0] Type R Reset value = 0100 0010 ...
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Si5368 Register 136. Bit D7 D6 Name RST_REG ICAL Type R/W R/W Reset value = 0000 0000 Bit Name 7 RST_REG RST_REG. Internal Reset. 0: Normal operation. 1: Reset of all internal logic. Outputs tristated or disabled during reset. 6 ...
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Register 138. Bit D7 D6 Name Reserved Type R Reset value = 0000 1111 Bit Name 7:4 Reserved Reserved. 3 LOS4_EN LOS4_EN [1:0]. [1:0] Note: LOS1_EN is split between two registers. 00: Disable LOS monitoring. 01: Reserved. 10: Enable LOSA ...
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Si5368 Register 139. Bit D7 D6 Name LOS4_EN LOS3_EN [0:0] [0:0] Type R/W R/W Reset value = 1111 1111 Bit Name 7 LOS4_EN LOS4_EN [0:0]. [0:0] Enable CKIN1 LOS Monitoring on the Specified Input (1 of 2). Note: LOS1_EN is ...
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FOS4_EN FOS4_EN. Enables FOS on a Per Channel Basis. 0: Disable FOS monitoring. 1: Enable FOS monitoring. 2 FOS3_EN FOS3_EN. Enables FOS on a Per Channel Basis. 0: Disable FOS monitoring. 1: Enable FOS monitoring. 1 FOS2_EN FOS2_EN. Enables ...
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Si5368 Register 141. Bit D7 D6 Name Type Reset value = 0000 0001 Bit Name 7:0 INDEPEND- INDEPENDENTSKEW2 [7:0]. ENTSKEW2 8 bit field that represents a twos complement of the phase offset in terms of clocks from [7:0] the high ...
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Register 144. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPEND- INDEPENDENTSKEW5 [7:0]. ENTSKEW5 8 bit field that represents a twos complement of the phase offset in terms of clocks from [7:0] the high speed ...
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Si5368 Table 4. CKOUT_ALWAYS_ON and SQICAL Truth Table CKOUT_ALWAYS_ON SQICAL Table 5 lists all of the register locations that should be followed by an ICAL after their contents are changed. Table 5. ...
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Table 5. Register Locations Requiring ICAL Addr Register 34 NC4_LS 37 NC5_LS 40 N2_HS 40 N2_LS 43 N31 46 N32 49 N33 51 N34 55 CLKIN2RATE 55 CLKIN1RATE 56 CLKIN4RATE 56 CLKIN3RATE Preliminary Rev. 0.41 Si5368 71 ...
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... Number Frequency Range Si5368A-C-GQ 2 kHz–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5368B-C-GQ 2 kHz–808 MHz Si5368C-C-GQ 2 kHz–346 MHz Note: Add the end of the device to denote tape and reel options (for example, Si5368-C-GMR). 72 Package ROHS6, Pb-Free 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Preliminary Rev ...
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Package Outline: 100-Pin TQFP Figure 4 illustrates the package details for the Si5368. Table 6 lists the values for the dimensions shown in the illustration. Figure 4. 100-Pin Thin Quad Flat Package (TQFP) Table 6. Dimension Min Nom A ...
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Si5368 7. Recommended PCB Layout 74 Figure 5. PCB Land Pattern Diagram Preliminary Rev. 0.41 ...
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Table 7. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ...
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Si5368 D C OCUMENT HANGE LIST Revision 0.1 to Revision 0.2 Changed LVTTL to LVCMOS in Table 2, “Absolute Maximum Ratings,” on page 6. Updated Figure 2 and Figure 3 on page 8. Updated “2. Pin Descriptions: ...
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N : OTES Preliminary Rev. 0.41 Si5368 77 ...
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