SI5324B-C-GMR Silicon Laboratories Inc, SI5324B-C-GMR Datasheet - Page 48

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SI5324B-C-GMR

Manufacturer Part Number
SI5324B-C-GMR
Description
IC CLOCK MULT 2KHZ-808MHZ 36VQFN
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5324B-C-GMR

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
36-VQFN
Frequency-max
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Si5324
Reset value = 0000 0000
48
Register 136.
Name
Type
5:0
Bit
Bit
7
6
RST_REG
RST_REG
R/W
Reserved
D7
Name
ICAL
ICAL
R/W
D6
Internal Reset (Same as Pin Reset).
Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.
0: Normal operation.
1: Reset of all internal logic. Outputs disabled or tristated during reset.
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence.
ICAL is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibra-
tion is complete once the LOL alarm goes low. A valid stable clock (within 100 ppm)
must be present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take
effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-cali-
bration, LOL will go low.
Reserved.
D5
Preliminary Rev. 0.3
D4
Function
D3
Reserved
R
D2
D1
D0

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