SI5368A-C-GQ Silicon Laboratories Inc, SI5368A-C-GQ Datasheet - Page 30

• Manufacturer Part Number: SI5368A-C-GQ
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368A-C-GQ

• Package / Case: 100-TQFP, 100-VQFP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Number Of Circuits: 1
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1417 MHz
• Supply Voltage (max): 2.75 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
Reset value = 1000 1000
30
Register 12.
Name
Type
Bit
Bit
7
6
5
4
3
SWTCH_REG
ALIGN_REG
FPW_VALID
FPW_
VALID
FSKEW_
FSYNC_
FSYNC_
FSYNC_
ALIGN_
MODE
Name
VALID
D7
FSYNC_
ALIGN_
FPW_VALID.
When in frame sync mode (CK_CONFIG_REG=1), before writing either a new
FSYNC_PW[9:0] or NC5_LS [19:0] value, this bit must be set to zero. This causes the
existing FSYNC_PW [9:0] or NC5_LS[19:0] value to be held by the internal state
machine for use while the new values are written. Once the new FSYNC_PW [9:0] or
NC5_LS [19:0] values are completely written, set FPW_VALID = 1 to enable their use.
0: Memorize existing FSYNC_PW[9:0] and NC5_LS [19:0] values and ignore
intermediate register values during write of new FSYNC_PW [9:0] and NC5_LS [19:0]
values.
1: Use FSYNC_PW[9:0] value directly from registers
FSYNC_ALIGN_REG.
If FSYNC_ALIGN_PIN=0, this bit controls realignment of FSYNCOUT to the active sync
input (CKIN_3 or CKIN_4). If FSYNC_ALIGN_PIN=1, the FSYNC_ALIGN pin controls
this function.
0: No realignment
1: Active
FSYNC_ALIGN_MODE.
This bit must be set to 1 when in frame sync mode (when CK_CONFIG_REG = 1).
FSYNC_SWTCH_REG.
Enables or disables the use of the CKIN3 and CKIN4 loss-of-signal indicators as inputs to
the automatic clock selection state machine for the clock configuration mode supporting
frame sync switching (CK_CONFIG=1 or CK_CONFIG_REG=1).
0: CKIN3 and CKIN4 status not used in clock selection
1: CKIN3 and CKIN4 status used in clock selection
FSKEW_VALID.
Before writing a new FSYNC_SKEW[16:0] value, this bit must be set to zero, which
causes the existing FSYNC_SKEW[16:0] value to be held internally by the skew
alignment state machine for use while the new value is being written. Once the new
FSYNC_SKEW[16:0] is completely written, set FSKEW_VALID=1 to enable its use.
0: Memorize existing FSYNC_SKEW[16:0] value and ignore intermediate register values
during write of new FSYNC_SKEW value.
1: Use FSYNC_SKEW[[16:0] value directly from registers.
REG
D6
FSYNC_
ALIGN_
MODE
D5
Preliminary Rev. 0.41
SWTCH_
FSYNC_
REG
D4
R/W
FSKEW_
Function
VALID
D3
FSYNC_
SKEW
[16:16]
D2
FSYNC_PW [9:8]
D1
D0