MC100H640FNR2 ON Semiconductor, MC100H640FNR2 Datasheet

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MC100H640FNR2

Manufacturer Part Number
MC100H640FNR2
Description
IC CLOCK DRIVER ECL-TTL 28-PLCC
Manufacturer
ON Semiconductor
Type
Buffer/Driverr
Datasheet

Specifications of MC100H640FNR2

Input
PECL, TTL
Output
TTL
Frequency - Max
135MHz
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Frequency-max
135MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100H640FNR2
Manufacturer:
ON Semiconductor
Quantity:
10 000
Part Number:
MC100H640FNR2
Quantity:
484
Part Number:
MC100H640FNR2G
Manufacturer:
ON Semiconductor
Quantity:
10 000
MC10H640, MC100H640
68030/040 PECL to TTL
Clock Driver
Description
68030, 68040 and similar microprocessors. It is guaranteed to meet the
clock specifications required by the 68030 and 68040 in terms of
part−to−part skew, within−part skew and also duty cycle skew.
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H640 also uses differential PECL internally to achieve its
superior skew characteristic.
to achieve the necessary duty cycle skew and to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Diagram).
Features
Function
outputs HIGH.
and ÷ 4 outputs synchronized at power up.
selects the TTL input source (DT).
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC10H/100H640 generates the necessary clocks for the
The user has a choice of using either TTL or PECL (ECL referenced
The H640 includes divide−by−two and divide−by−four stages, both
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
Power−Up: The device is designed to have the POS edges of the ÷ 2
Select (SEL): LOW selects the ECL input source (DE/DE). HIGH
The H640 also contains circuitry to force a stable state of the ECL
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0 V Supply
Pb−Free Packages are Available*
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
xxx
A
WL
YY
WW
G
MARKING DIAGRAM*
http://onsemi.com
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MCxxxH640G
FN SUFFIX
CASE 776
PLCC−28
AWLYYWW
Publication Order Number:
1
MC10H640/D

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MC100H640FNR2 Summary of contents

Page 1

... In this case, the DE side of the input is pulled LOW, and DE goes HIGH. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − ...

Page 2

Figure 1. Pinout: ...

Page 3

Table 3. 10H PECL DC CHARACTERISTICS Symbol Characteristic I Input HIGH Current INH I Input LOW Current INL V 1 Input HIGH Voltage Input LOW Voltage Output Reference Voltage BB NOTE: Device will meet ...

Page 4

Table 6. AC CHARACTERISTICS (V Symbol Characteristic t Propagation Delay ECL PLH D to Output t Propagation Delay TTL PLH D to Output tskwd* Within−Device Skew t Propagation Delay ECL PLH D to Output t Propagation Delay TTL PLH D ...

Page 5

To maintain a duty cycle of ± 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 3 and 4. For a ± 2.5% duty cycle limit, see Figures 5 and 6. Figures 7 and ...

Page 6

Figure RESET tpw Q0, Q1, Q2, Q3 Q0, Q1 Q4, Q5 Figure 10. MC10H/100H640 Clock Phase and Reset Recovery Time After Reset Pulse → Q ...

Page 7

... ORDERING INFORMATION Device MC10H640FN MC10H640FNG MC10H640FNR2 MC10H640FNR2G MC100H640FN MC100H640FNG MC100H640FNR2 MC100H640FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D − ...

Page 8

0.010 (0.250) T L− NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...

Page 9

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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