SY89874UMG Micrel Inc, SY89874UMG Datasheet - Page 5

IC CLK DVDR ANYDIFF-LVPECL 16MLF

SY89874UMG

Manufacturer Part Number
SY89874UMG
Description
IC CLK DVDR ANYDIFF-LVPECL 16MLF
Manufacturer
Micrel Inc
Series
Precision Edge®r
Type
Fanout Buffer (Distribution), Dividerr
Datasheet

Specifications of SY89874UMG

Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Input
CML, HSTL, LVDS, LVPECL
Output
LVPECL
Frequency - Max
2.5GHz
Voltage - Supply
2.375 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-MLF®, QFN
Frequency-max
2.5GHz
Clock Ic Type
Clock Driver / Fanout Buffer
Frequency
2.5GHz
No. Of Outputs
2
No. Of Multipliers / Dividers
4
Supply Current
50mA
Supply Voltage Range
2.375V To 3.63V
Digital Ic Case
RoHS Compliant
Function
Clock Divider
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
MLF
Pin Count
16
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-1437

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SY89874UMG
Manufacturer:
Micrel Inc
Quantity:
1 884
V
Symbol
f
t
t
t
T
t
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
M9999-031208
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
MAX
PD
SKEW
RR
r
,t
CC
jitter
AC ELECTRICAL CHARACTERISTICS
f
TIMING DIAGRAM
= 3.3V 10% or 2.5V 5%; T
Measured with 400mV input signal, 50% duty cycle, all outputs loaded with 50 to V
Specification for packaged product only.
Skew is measured between outputs under identical transitions.
See “Timing Diagram.”
Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T
where T is the time between rising edges of the output signal.
Total jitter definition: with an ideal clock input, of frequency f
than the specified peak-to-peak jitter value.
Parameter
Maximum Output Toggle Frequency
Maximum Input Frequency
Differential Propagation Delay
IN to Q
Within-Device Skew (diff.)
Q0–Q1
Part-to-Part Skew (diff.)
Reset Recovery Time
Cycle-to-Cycle Jitter
Total Jitter
Rise/Fall Time (20% to 80%)
/RESET
/IN
A
/Q
IN
Q
= –40 C to +85 C; Unless otherwise stated.
V
IN
V
Swing
IN
Condition
Output Swing
Divide by 2, 4, 8, 16
Input Swing < 400mV
Input Swing
Note 3
Note 3
Note 4
Note 5
Note 6
(Notes 1, 2)
MAX
(device), no more than one output edge in 10
5
400mV
400mV
V
t
CC/2
RR
CC
–2V, unless otherwise stated.
t
PD
V
OUT
Min
540
480
600
2.5
3.2
Swing
70
12
output edges will deviate by more
Typ
650
600
150
7
Precision Edge
Max
790
730
250
250
15
10
1
jitter_cc
SY89874U
=T
ps
n
Units
ps
–T
GHz
GHz
ps
ps
ps
ps
ps
ps
RMS
PP
n+1
®
,

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