SI5330B-A00204-GM Silicon Laboratories Inc, SI5330B-A00204-GM Datasheet - Page 12

• Manufacturer Part Number: SI5330B-A00204-GM
• Description: IC BUFFER LVDS DIFF 4OUT 24-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Fanout Buffer (Distribution), Translatorr

Specifications of SI5330B-A00204-GM

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: CML, CMOS, HCSL, HSTL, LVDS, LVPECL, LVTTL, SSTL
• Output: LVDS
• Frequency - Max: 710MHz
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Frequency-max: 710MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1550-5

Si5330
12
Pin #
14
15
16
17
18
19
Pin Name
VDDO2
VDDO1
CLK2A
CLK1B
CLK1A
OEB
Table 9. Si5330 Pin Descriptions (Continued)
VDD
VDD
I/O
O
O
O
I
Signal Type
Supply
Supply
CMOS
Multi
Multi
Multi
Rev. 0.35
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK2 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK2 outputs. Both
CLK2A and CLK2B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Output Clock Supply Voltage.
Supply voltage for CLK2A/B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK2 is not used, this
pin must be tied to V
Output Clock Supply Voltage.
Supply voltage for CLK1A,B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK1 is not used, this
pin must be tied to V
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
Output Enable.
All outputs are enabled when the OEB pin is connected
to ground or below the V
ing the OEB pin to V
able the outputs. Both V
Table 7. All outputs are forced to a logic “low” when dis-
abled. This pin is 3.3 V tolerant.
DD
DD
DD
Description
or above the V
(pin 7 and/or pin 24).
(pin 7 and/or pin 24).
IL
IL
and V
voltage for this pin. Connect-
IH
are specified in
IH
level will dis-