NB6L11DG ON Semiconductor, NB6L11DG Datasheet - Page 7

• Manufacturer Part Number: NB6L11DG
• Description: IC BUFFER/XLATOR DIFF 1:2 8-SOIC
• Manufacturer: ON Semiconductor
• Type: Fanout Buffer (Distribution), Translatorr

Specifications of NB6L11DG

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, LVCMOS, LVDS, LVNECL, LVPECL, LVTTL
• Output: ECL
• Frequency - Max: 6GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 6GHz
• Number Of Outputs: 4
• Operating Supply Voltage (max): -3.465/3.465V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.22ns
• Operating Supply Voltage (min): -2.375/2.375V
• Mounting: Surface Mount
• Pin Count: 8
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Package Type: SOIC N
• Input Frequency: >6000MHz
• Operating Temperature Classification: Industrial
• Max Input Freq: >6000 MHz
• Propagation Delay (max): 0.2 ns @ 2.375V to 3.465V
• Supply Voltage (max): - 3.465 V or 3.465 V
• Supply Voltage (min): - 2.375 V or 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NB6L11DG; NB6L11DGOS

Table 7. AC CHARACTERISTICS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
23. Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to V
24. See Figure 13 t
25. Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
26. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2
27. V
Symbol
V
f
t
t
t
t
V
t
t
DATA
PLH
PHL
SKEW
JITTER
r
f
OUTPP
INPP
transitions and conditions @ 1 GHz.
operating in differential mode
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
,
INPP(max)
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
Figure 2. Output Voltage Amplitude (V
Output Voltage Amplitude
(See Figures 2 &
Maximum Operating Data Rate
Propagation Delay to
Output Differential @ 1 GHz
Duty Cycle Skew
Within Device Skew
Device−to−Device Skew
RMS Random Clock Jitter
(Note 25)
Peak−to−Peak Data Dependent Jitter
(Note 26)
Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 27)
Output Rise/Fall Times @ 1 GHz
versus Input Clock Frequency (f
1
(20% − 80%)
cannot exceed V
Temperature at V
INPUT CLOCK FREQUENCY (GHz)
skew
2
= |t
PLH
25°C
Characteristic
3
3)
− t
CC
PHL
− V
4
| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
85°C
CC
EE
V
− V
(applicable only when V
CC
5
EE
= 0 V; V
−40°C
= 3.3 V
f
f
f
f
in
in
in
in
6
IN
D to Q, Q
v 6 Gb/s
(Note 24)
v 3 GHz
v 6 GHz
v 6 GHz
EE
) and
OUTPP
= −3.465 V to −2.375 V or V
Q, Q
7
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)
CC
Min
480
270
110
75
30
8
6
23
− V
7
−1 data rate at 6 Gb/s.
EE
−40°C
Typ
700
300
150
700
0.2
15
75
2
5
2
< 2500 mV). Input voltage swing is a single−ended measurement
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2500
Max
190
120
10
15
60
12
1
Figure 3. Output Voltage Amplitude (V
CC
versus Input Clock Frequency (f
1
= 2.375 V to 3.465 V; V
Min
480
270
110
75
30
Temperature at V
INPUT CLOCK FREQUENCY (GHz)
CC
2
− 2.0 V. Input edge rates 40 ps (20% − 80%).
25°C
Typ
700
300
150
700
0.2
15
75
2
5
2
25°C
3
2500
Max
200
120
10
15
60
12
1
4
−40°C
85°C
CC
EE
Min
480
270
120
75
30
− V
= 0 V (Note 23)
5
EE
85°C
Typ
700
300
160
700
0.2
15
75
2
5
2
= 2.5 V
6
IN
2500
Max
220
120
) and
10
15
60
12
1
OUTPP
7
Gb/s
Unit
mV
mV
ps
ps
ps
ps
)
8