ICS8535AGI-31LF IDT, Integrated Device Technology Inc, ICS8535AGI-31LF Datasheet - Page 6

• Manufacturer Part Number: ICS8535AGI-31LF
• Description: IC CLK FAN BUFF MUX 1:4 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS8535AGI-31LF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: No/Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVPECL
• Frequency - Max: 266MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 266MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1960-5; 8535AGI-31LF; ICS8535AGI-31LF

ICS8535I-31
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value
of the fundamental. This ratio is expressed in decibels (dBm) or a
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
ICS8535AGI-31 REVISION A JANUARY 27, 2010
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1k
10k
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
100k
Offset Frequency (Hz)
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ratio of the power in the 1Hz band to the power in the fundamental.
When the required offset is specified, the phase noise is called a dBc
value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain, we get
a better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
1M
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.057ps (typical)
©2010 Integrated Device Technology, Inc.
10M
100M