PCK2001RDB,112 NXP Semiconductors, PCK2001RDB,112 Datasheet - Page 5

• Manufacturer Part Number: PCK2001RDB,112
• Description: IC 1:6 CLOCK BUFFER 16SSOP
• Manufacturer: NXP Semiconductors
• Type: Fanout Buffer (Distribution)r

Specifications of PCK2001RDB,112

• Package / Case: 16-SSOP
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: No/No
• Input: LVTTL
• Output: LVTTL
• Frequency - Max: 533MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 533MHz
• Number Of Outputs: 6
• Max Input Freq: 533 MHz
• Propagation Delay (max): 2.6 ns
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Power Dissipation: 850 mW
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935268179112; PCK2001RDB; PCK2001RDB

Philips Semiconductors
AC CHARACTERISTICS
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5V.
2. t
3. t
4. t
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to
9. All typical values are at V
10. Typical is measured with MAX (30pF) discrete load.
11. Typical is measured with MIN (20pF) discrete load.
2002 Dec 13
DUTY CYCLE
533 MHz I
ensure duty cycle specification is met.
SYMBOL
SYMBOL
H
L
SDRISE
t
t
t
SDRISE
SDFALL
DDSKW
is measured at 0.4V as shown in Figure 2.
is measured at 2.4V as shown in Figure 2.
t
t
t
SKW
PLH
PHL
t
t
t
t
t
t
t
t
t
t
t
t
H
H
H
H
P
L
P
L
P
L
P
L
and t
SDFALL
2
C 1:6 clock buffer
Buffer LH propagation delay
Buffer HL propagation delay
are measured as a transition through the threshold region V
Device to device skew
CC
Output Duty Cycle
CLK HIGH time
CLK HIGH time
CLK HIGH time
CLK HIGH time
CLK LOW time
CLK LOW time
CLK LOW time
CLK LOW time
Bus CLK skew
PARAMETER
PARAMETER
= 3.3V and T
CLK period
CLK period
CLK period
CLK period
Rise time
Fall time
amb
= 25°C.
Measured at 1.5 V
TEST CONDITIONS
100 MHz
133 MHz
33 MHz
66 MHz
5
NOTES
4, 6, 10
4, 6, 11
2, 6, 8
3, 6, 8
2, 6, 8
3, 6, 8
2, 6, 8
3, 6, 8
2, 6, 8
3, 6, 8
5, 6, 7
OL
1, 6
1, 6
1, 6
1, 6
1,6
6, 7
6, 7
= 0.4V and V
29.9
12.3
12.1
14.9
MIN
5.6
5.3
9.9
3.3
3.2
7.4
2.6
2.2
1.5
1.5
1.0
1.0
45
OH
T
amb
= 2.4V (1 mA) JEDEC specification.
= 0°C to +70°C
LIMITS
10.01
TYP
30.0
14.3
14.1
15.0
150
6.8
6.5
4.2
4.1
7.5
3.1
2.7
2.0
2.5
2.4
2.6
50
9
PCK2001R
MAX
30.2
16.3
16.1
15.2
10.2
250
500
8.0
7.7
5.1
5.0
7.7
3.6
3.2
4.0
4.0
3.5
3.5
55
Product data
UNIT
UNIT
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ps
ps
%