ADCLK950BCPZ Analog Devices Inc, ADCLK950BCPZ Datasheet - Page 6

• Manufacturer Part Number: ADCLK950BCPZ
• Description: IC CLK FAN BUFF MUX 2:10 40LFCSP
• Manufacturer: Analog Devices Inc
• Series: SIGer
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ADCLK950BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:10
• Differential - Input:output: Yes/Yes
• Input: CML, CMOS, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 4.8GHz
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Frequency-max: 4.8GHz
• Clock Ic Type: Clock Buffer
• Frequency: 4.8GHz
• No. Of Outputs: 10
• Supply Current: 346mA
• Supply Voltage Range: 2.97V To 3.63V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADCLK950
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11, 20, 21,
30, 31, 40
12, 13
14, 15
16, 17
18, 19
22, 23, 28,
29
24, 25
26, 27
32, 33
34, 35
36, 37
38, 39
Mnemonic
IN_SEL
CLK0
CLK0
V
V
CLK1
CLK1
V
V
V
V
Q9, Q9
Q8, Q8
Q7, Q7
Q6, Q6
NC
Q5, Q5
Q4, Q4
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
EPAD
T
REF
EE
CC
REF
T
0
1
1
0
Description
Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.
Differential Input (Positive) 0.
Differential Input (Negative) 0.
Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.
Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.
Differential Input (Positive) 1.
Differential Input (Negative) 1.
Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.
Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.
Negative Supply Pin.
Positive Supply Pin.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
No Connection
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Exposed pad (EPAD) must be connected to V
IN_SEL
NOTES
1. NC = NO CONNECT.
2. EPAD MUST BE SOLDERED TO V
V
V
CLK0
CLK0
CLK1
CLK1
REF
REF
V
V
V
EE
T
T
0
0
1
1
10
1
2
3
4
5
6
7
8
9
Figure 2. Pin Configuration
PIN 1
INDICATOR
Rev. A | Page 6 of 12
ADCLK950
(Not to Scale)
TOP VIEW
EE
POWER PLANE.
EE
.
30 V
29 NC
28 NC
27 Q4
26 Q4
25 Q5
24 Q5
23 NC
22 NC
21 V
CC
CC