ICS85211AMI-01LFT IDT, Integrated Device Technology Inc, ICS85211AMI-01LFT Datasheet

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ICS85211AMI-01LFT

Manufacturer Part Number
ICS85211AMI-01LFT
Description
IC FANOUT BUFFER 1-2 8-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of ICS85211AMI-01LFT

Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
Yes/Yes
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
HSTL
Frequency - Max
700MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC
Frequency-max
700MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
85211AMI-01LFT

Available stocks

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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS85211AMI-01LFT
Quantity:
3 000
B
85211AMI-01
G
The ICS85211I-01 is a low skew, high performance 1-to-2
Differential-to-HSTL Fanout Buffer. The CLK, nCLK pair can
accept most standarddifferential input levels.The ICS85211I-
01 is characterized to operate from a 3.3V power supply.
Guaranteed output and part-to-part skew characteristics
make the ICS85211I-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability. For optimal performance, terminate all outputs.
LOCK
ENERAL
nCLK
CLK
D
IAGRAM
D
ESCRIPTION
Q0
nQ0
Q1
nQ1
www.idt.com
1
F
P
Two differential HSTL compatible outputs
One differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
Maximum output frequency: 700MHz
Translates any single-ended input signal to HSTL
levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 1ns (maximum)
Output crossover Voltage: 0.68V to 0.9V
Output duty cycle: 49% - 51% up to 266.6MHz
V
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
EATURES
IN
OH
D
= 1.4V (maximum)
A
IFFERENTIAL
3.90mm x 4.90mm x 1.37mm package body
SSIGNMENT
nQ0
nQ1
Q0
Q1
ICS85211I-01
-
TO
8-Lead SOIC
M Package
1
2
3
4
Top View
-HSTL F
ICS85211I-01
8
7
6
5
L
V
CLK
nCLK
GND
OW
DD
ANOUT
S
KEW
REV. B AUGUST 4, 2010
, 1-
B
UFFER
TO
-2

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ICS85211AMI-01LFT Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS85211I- low skew, high performance 1-to-2 Differential-to-HSTL Fanout Buffer. The CLK, nCLK pair can accept most standarddifferential input levels.The ICS85211I characterized to operate from a 3.3V power supply. Guaranteed output and ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 4A ABLE ...

Page 4

3.3V ± 5%, T ABLE HARACTERISTICS ...

Page 5

P ARAMETER 3.3V± HSTL GND 0V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy t sk( UTPUT KEW 80% Clock 20% Outputs UTPUT ISE ...

Page 6

IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...

Page 7

R U ECOMMENDATIONS FOR NUSED O : UTPUTS HSTL O UTPUT All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or ...

Page 8

This section provides information on power dissipation and junction temperature for the ICS85211I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85211I-01 is the sum of the core power plus the power ...

Page 9

Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 4. F IGURE T o calculate worst case power dissipation into the ...

Page 10

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second ...

Page 11

ACKAGE UTLINE UFFIX FOR EAD T ABLE S Y Reference Document: JEDEC Publication 95, MS-012 85211AMI-01 D IFFERENTIAL SOIC ACKAGE IMENSIONS ...

Page 12

ABLE RDERING NFORMATION ...

Page 13

...

Page 14

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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