MC100LVEP14DTR2G ON Semiconductor, MC100LVEP14DTR2G Datasheet

MC100LVEP14DTR2G

Manufacturer Part Number

MC100LVEP14DTR2G

Description

IC CLOCK DRIVER 1:5 DFF 20-TSSOP

Manufacturer

ON Semiconductor

Series

100LVEPr

Type

Fanout Buffer (Distribution), Multiplexerr

Datasheet

1.MC100LVEP14DTR2G.pdf (7 pages)

Specifications of MC100LVEP14DTR2G

Number Of Circuits

Ratio - Input:output

2:5

Differential - Input:output

Yes/Yes

Input

ECL, HSTL, LVDS, PECL

Output

ECL, PECL

Frequency - Max

2.5GHz

Voltage - Supply

2.375 V ~ 3.8 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-TSSOP

Frequency-max

2.5GHz

Number Of Clock Inputs

Mode Of Operation

Differential

Output Logic Level

ECL/PECL

Operating Supply Voltage (min)

-2.375/2.375V

Operating Supply Voltage (typ)

-2.5/-3.3/2.5/3.3V

Operating Supply Voltage (max)

-3.8/3.8V

Package Type

TSSOP

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Signal Type

ECL/HSTL/PECL

Mounting

Surface Mount

Pin Count

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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MC100LVEP14

2.5V / 3.3V 1:5 Differential

ECL/PECL/HSTL Clock Driver

Description

with clock distribution in mind, accepting two clock sources into an input

multiplexer. The ECL/PECL input signals can be either differential or

single−ended (if the V

the LVEP14 is operating under PECL conditions.

Optimal design, layout, and processing minimize skew within a device and

from device to device.

any differential output need to be terminated identically into 50 W

even if only one output is being used. If an output pair is unused, both

outputs may be left open (unterminated) without affecting skew.

disabled in the LOW state. This avoids a runt clock pulse when the

device is enabled/disabled as can happen with an asynchronous

control. The internal flip flop is clocked on the falling edge of the input

clock; therefore, all associated specification limits are referenced to

the negative edge of the clock input.

operated from a positive V

LVEP14 to be used for high performance clock distribution in +3.3 V

or +2.5 V systems. Single−ended CLK input pin operation is limited to

a V

Designers can take advantage of the LVEP14’s performance to

distribute low skew clocks across the backplane or the board.

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

June, 2010 − Rev. 13

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100LVEP14 is a low skew 1−to−5 differential driver, designed

The LVEP14 specifically guarantees low output−to−output skew.

To ensure that the tight skew specification is realized, both sides of

The common enable (EN) is synchronous, outputs are enabled/

The MC100LVEP14, as with most other ECL devices, can be

100 ps Device−to−Device Skew

25 ps Within Device Skew

400 ps Typical Propagation Delay

Maximum Frequency > 2 GHz Typical

The 100 Series Contains Temperature Compensation

PECL and HSTL Mode:

NECL Mode:

LVDS Input Compatible

Open Input Default State

Pb−Free Packages are Available*

≥ 3.0 V in PECL mode, or V

= 2.375 V to 3.8 V with V

= 0 V with V

= −2.375 V to −3.8 V

output is used). HSTL inputs can be used when

supply in PECL mode. This allows the

= 0 V

≤ −3.0 V in NECL mode.

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*For additional marking information, refer to

Application Note AND8002/D.

(Note: Microdot may be in either location)

ORDERING INFORMATION

MARKING DIAGRAM*

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

CASE 948E

DT SUFFIX

TSSOP−20

ALYWG

VP14

100

Publication Order Number:

MC100LVEP14/D

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MC100LVEP14DTR2G Summary of contents

Page 1

... Open Input Default State • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2010 June, 2010 − Rev. 13 ≤ −3 NECL mode. ...

Page 2

Warning: All V to Power Supply to guarantee proper operation. Figure 1. 20−Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION Pin Type CLK0*, LVECL/LVPECL/ ECL/PECL/HSTL CLK Input ...

Page 3

Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...

Page 4

Table 6. 100LVEP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...

Page 5

Table 8. DC CHARACTERISTICS, HSTL Symbol Characteristic V Input HIGH Voltage IH V Input LOW Voltage IL NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with ...

Page 6

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEP14DT MC100LVEP14DTG MC100LVEP14DTR2 MC100LVEP14DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. 5.0 V 3.3 V ...

Page 7

... PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...

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