GTLP6C816MTCX Fairchild Semiconductor, GTLP6C816MTCX Datasheet

GTLP6C816MTCX

Manufacturer Part Number

GTLP6C816MTCX

Description

IC CLK DRIVER GTLP-TTL 24-TSSOP

Manufacturer

Fairchild Semiconductor

Type

Fanout Buffer (Distribution)r

Datasheet

1.GTLP6C816MTC.pdf (6 pages)

Specifications of GTLP6C816MTCX

Number Of Circuits

Ratio - Input:output

1:2, 1:6

Differential - Input:output

No/No

Input

GTLP, TTL

Output

GTLP, TTL

Voltage - Supply

4.75 V ~ 5.25 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

24-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Frequency-max

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

GTLP6C816MTCX

Manufacturer:

FAIRCHILD/仙童

Quantity:

20 000

Current page: 1 of 6
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GTLP6C816MTC

TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)

OEB

OEA

GNDG

OA0–OA5

OB0–OB1

GTLP6C816

GTLP/TTL 1:6 Clock Driver

General Description

The GTLP6C816 is a clock driver that provides TTL to

GTLP signal level translation (and vice versa). The device

provides a high speed interface between cards operating at

TTL logic levels and a backplane operating at GTLP logic

levels. High speed backplane operation is a direct result of

GTLP’s reduced output swing ( 1V), reduced input thresh-

old levels and output edge rate control. The edge rate con-

trol minimizes bus settling time. GTLP is a Fairchild

Semiconductor derivative of the Gunning Transceiver logic

(GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is pro-

cess, voltage, and temperature (PVT) compensated. Its

function is similar to BTL and GTL but with different output

levels and receiver threshold. GTLP output LOW level is

typically less than 0.5V, the output level HIGH is 1.5V and

the receiver threshold is 1.0V.

Ordering Code:

Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pin Descriptions

Order Number

CCT

REF

Pin Names

.GNDT

Output Enable (Active LOW)

GTLP Port (TTL Levels)

Output Enable (Active LOW)

TTL Port (TTL Levels)

TTL Output Supplies (5V)

Internal Circuitry V

OBn GTLP Output Grounds

Voltage Reference Input

TTL Buffered Clock Outputs

GTLP Buffered Clock Outputs

Package Number

MTC24

Description

(5V)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

DS500129

Features

Connection Diagram

Interface between LVTTL and GTLP logic levels

Designed with edge rate control circuitry to reduce out-

put noise on the GTLP port

receiver threshold adjustibility

Special PVT compensation circuitry to provide consis-

tent performance over variations of precess, supply volt-

age and temperature

TTL compatible driver and control inputs

Designed using Fairchild advanced CMOS technology

Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

Power up/down and power off high impedance for live

insertion

5V over voltage tolerance on LVTTL ports

Open drain on GTLP to support wired-or connection

A Port source/sink 24mA/ 24mA

B Port sink 50mA

1:6 fanout clock driver for TTL port

1:2 fanout clock driver for GTLP port

REF

Package Description

pin provides external supply reference voltage for

June 1998

Revised December 2000

www.fairchildsemi.com

Related parts for GTLP6C816MTCX

GTLP6C816MTCX Summary of contents

Page 1

... Voltage Reference Input REF OA0–OA5 TTL Buffered Clock Outputs OB0–OB1 GTLP Buffered Clock Outputs © 2000 Fairchild Semiconductor Corporation Features Interface between LVTTL and GTLP logic levels Designed with edge rate control circuitry to reduce out- put noise on the GTLP port V ...

Page 2

Functional Description The GTLP6C816 is a clock driver providing TTL-to-GTLP clock translation, and GTLP-to-TTL clock translation in the same package. The TTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to-TTL direc- tion ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 2) DC Output Sink Current into OA Port Output Source Current from ...

Page 4

DC Electrical Characteristics Symbol Test Conditions C Control Pins/GTLPIN/ IN TTLIN C OAn Port OUT OBn Port Note 4: All typical values are at V 5.0V and Note 5: GTLP V and V are specified ...

Page 5

Test Circuit and Timing Waveforms Test Circuit for A Outputs Note A: C includes probes and jig capacitance. L Voltage Waveforms Enable and Disable Times A Port Voltage Waveforms Propagation Delay (V Test Circuit for B Outputs Note A: C ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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