MC100E111FNR2 ON Semiconductor, MC100E111FNR2 Datasheet

MC100E111FNR2

Manufacturer Part Number

MC100E111FNR2

Description

IC CLOCK DRIVER 1:9 DIFF 28-PLCC

Manufacturer

ON Semiconductor

Series

100Er

Type

Fanout Buffer (Distribution)r

Datasheet

1.MC100E111FNR2G.pdf (10 pages)

Specifications of MC100E111FNR2

Number Of Circuits

Ratio - Input:output

1:9

Differential - Input:output

Yes/Yes

Input

ECL, PECL

Output

ECL, PECL

Frequency - Max

800MHz

Voltage - Supply

4.2 V ~ 5.7 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

28-PLCC

Frequency-max

800MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MC100E111FNR2

Manufacturer:

ON Semiconductor

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

MC100E111FNR2

Manufacturer:

ON/安森美

Quantity:

20 000

Company:

BOSTOCK HK LIMITED

Part Number:

MC100E111FNR2G

Manufacturer:

ON Semiconductor

Quantity:

10 000

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MC10E111, MC100E111

5V ECL 1:9 Differential

Clock Driver

Description

designed with clock distribution in mind. It accepts one signal input,

which can be either differential or else single-ended if the V

is used. The signal is fanned out to 9 identical differential outputs. An

enable input is also provided. A HIGH disables the device by forcing

all Q outputs LOW and all Q outputs HIGH.

skew as the key goal. Optimal design and layout serve to minimize

gate to gate skew within-device, and empirical modeling is used to

determine process control limits that ensure consistent t

distributions from lot to lot. The net result is a dependable, guaranteed

low skew device.

pair, and the greatest TPD delay time results from terminating all the

output pairs. This shift is about 10 – 20 pS in TPD. The skew between

any two output pairs within a device is typically about 25 nS. If other

output pairs are not terminated, the lowest TPD delay time results

from both output pairs and the skew is typically 25 nS. When all

outputs are terminated, the greatest TPD (delay time) occurs and all

outputs display about the same 10 – 20 pS increase in TPD, so the

relative skew between any two output pairs remains about 25 nS.

this device only. For single-ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

November, 2006 − Rev. 16

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC10E/100E111 is a low skew 1-to-9 differential driver,

The device is specifically designed, modeled and produced with low

The lowest TPD delay time results from terminating only one output

The V

The 100 Series contains temperature compensation.

PECL Mode Operating Range: V

NECL Mode Operating Range: V

Internal Input 50 KW Pulldown Resistors

ESD Protection: Human Body Model; > 3 kV

Meets or Exceeds JEDEC Standard EIA/JESD78 IC

Latchup Test

Guaranteed Skew Spec

Differential Design

with V

may also rebias AC coupled inputs. When used, decouple V

Output

via a 0.01 mF capacitor and limit current sourcing or sinking

pin, an internally generated voltage supply, is available to

= 0 V

= −4.2 V to −5.7 V

should be left open.

as a switching reference voltage.

= 4.2 V to 5.7 V

= 0 V

output

•

Moisture Sensitivity Level:

For Additional Information, see Application Note

AND8003/D

Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

Transistor Count = 178 devices

Pb−Free Packages are Available*

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

Pb = 1

Pb−Free = 3

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

xxx

MARKING DIAGRAM*

http://onsemi.com

MCxxxE111G

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

AWLYYWW

FN SUFFIX

CASE 776

PLCC−28

Publication Order Number:

MC10E111/D

Related parts for MC100E111FNR2

MC100E111FNR2 Summary of contents

Page 1

... ESD Protection: Human Body Model; > • Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 16 output ...

Page 2

CCO Pinout: 28-Lead PLCC (Top View ...

Page 3

Table 2. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature Range A T Storage Temperature Range ...

Page 4

Table 3. 10E SERIES PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

Page 5

Table 5. 100E SERIES PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

Page 6

Table 7. AC CHARACTERISTICS V CCx Symbol Characteristic f Maximum Toggle Frequency MAX t Propagation Delay to Output PLH t IN (Diff) (Note 14) PHL IN (SE) (Note 15) Enable (Note 16) Disable (Note 16) t Setup Time (Note 17) ...

Page 7

900 800 700 600 500 400 300 200 É É É (JITTER) 100 É É É É É É É É É É É É É É É É É É É É É É 300 600 900 ...

Page 8

... ORDERING INFORMATION Device MC10E111FN MC10E111FNG MC10E111FNR2 MC10E111FNR2G MC100E111FN MC100E111FNG MC100E111FNR2 MC100E111FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D − ...

Page 9

0.010 (0.250) T L− NOTES: 1. DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...

Page 10

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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