MC100E211FN ON Semiconductor, MC100E211FN Datasheet - Page 8

• Manufacturer Part Number: MC100E211FN
• Description: IC CLOCK DISTR 1:6 DIFF 28-PLCC
• Manufacturer: ON Semiconductor
• Series: 100Er
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MC100E211FN

• Number Of Circuits: 1
• Ratio - Input:output: 2:6
• Differential - Input:output: Yes/Yes
• Input: ECL, PECL
• Output: ECL, PECL
• Frequency - Max: 700MHz
• Voltage - Supply: 4.2 V ~ 5.7 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Differential versus Single−Ended Use
of the E211 the device must be used in the differential mode.
In the single−ended mode the propagation delays are
dependent on the relative position of the V
reference. Any V
will add delay to either the T
from the other. This increase and decrease in delay will lead
to an increase in the duty cycle skew and thus part−to−part
skew. The within−device skew will be independent of the
V
device is driven differentially or single−ended.
skew are not important the advantages of single−ended
clock distribution may lead to its use. Using single−ended
interconnect will reduce the number of signal traces to be
routed, but remember that all of the complementary outputs
still need to be terminated therefore there will be no
reduction in the termination components required. To use
the E211 with a single−ended input the arrangement pictured
in Figure 5 should be used. If the input to the differential
CLK inputs are AC coupled as pictured in Figure 4 the
dependence on a centered V
situation pictured will ensure that the input is centered
around the bias set by the V
the AC specification limits for a differential input can be
used. For more information on AC coupling please refer to
the interfacing section of the design guide in the ECLinPS
data book.
Using the Enable Pins
enables (ENx) are synchronous to the CLK or SCLK input
depending on which is selected. The active low signals are
clocked into the enable flip flops on the negative edges of the
E211 clock inputs. In this way the devices will only be
disabled when the outputs are already in the LOW state. The
internal propagation delays are such that the delay to the
output through the distribution buffers is less than that
through the enable flip flops. This will ensure that the
disabling of the device will not slice any time off the clock
pulse. On initial power up the enable flip flops will randomly
attain a stable state, therefore precautions should be taken on
initial power up to ensure the E211 is in the desired state.
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As can be seen from the data sheet, to minimize the skew
For applications where part−to−part skew or duty cycle
Both the common enable (CEN) and the individual
and therefore will be the same regardless of whether the
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offset from the center of the input swing
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PLH
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. As a result when AC coupled
reference is removed. The
or T
PHL
and subtract delay
APPLICATIONS INFORMATION
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switching
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IN
0.001mF
IN
IN
IN
Figure 5. Single−Ended Input
Figure 4. AC Coupled Input
V
V
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50 W
0.01 mF
0.01mF