MC100E310FNR2 ON Semiconductor, MC100E310FNR2 Datasheet

MC100E310FNR2

Manufacturer Part Number

MC100E310FNR2

Description

IC BUFFER FANOUT 2:8 DIFF 28PLCC

Manufacturer

ON Semiconductor

Series

100Er

Type

Fanout Buffer (Distribution), Multiplexerr

Datasheet

1.MC100E310FNR2G.pdf (8 pages)

Specifications of MC100E310FNR2

Number Of Circuits

Ratio - Input:output

2:8

Differential - Input:output

Yes/Yes

Input

ECL, PECL

Output

ECL, PECL

Frequency - Max

900MHz

Voltage - Supply

4.2 V ~ 5.7 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

28-PLCC

Frequency-max

900MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

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Part Number:

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Company:

BOSTOCK HK LIMITED

Part Number:

MC100E310FNR2

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Quantity:

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Company:

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Part Number:

MC100E310FNR2G

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MC100E310

5V ECL Low Voltage 2:8

Differential Fanout Buffer

Description

fanout buffer designed with clock distribution in mind. The device

features fully differential clock paths to minimize both device and

system skew. The E310 offers two selectable clock inputs to allow for

redundant or test clocks to be incorporated into the system clock trees.

pair, and the greatest TPD delay time results from terminating all the

output pairs. This shift is about 10−20 pS in TPD. The skew between

any two output pairs within a device is typically about 25 nS. If other

output pairs are not terminated, the lowest TPD delay time results

from both output pairs and the skew is typically 25 nS. When all

outputs are terminated, the greatest TPD (delay time) occurs and all

outputs display about the same 10 − 20 ps increase in TPD, so the

relative skew between any two output pairs remains about 25 ns.

ON Semiconductor Application Note AN1406/D.

this device only. For single-ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

January, 2009 − Rev. 6

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100E310 is a low voltage, low skew 2:8 differential ECL

The lowest TPD delay time results from terminating only one output

For more information on using PECL, designers should refer to

The V

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range: V

NECL Mode Operating Range: V

Internal Input 50 kW Pulldown Resistors

ESD Protection: Human Body Model; >2 kV,

Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

Dual Differential Fanout Buffers

200 ps Part−to−Part Skew

50 ps Output−to−Output Skew

28−lead PLCC Packaging

Q Output will Default LOW with Inputs Open or at V

with V

may also rebias AC coupled inputs. When used, decouple V

via a 0.01 mF capacitor and limit current sourcing or sinking

pin, an internally generated voltage supply, is available to

= 0 V

= −4.2 V to −5.7 V

Machine Model; >200 V

should be left open.

as a switching reference voltage.

= 4.2 V to 5.7 V

= 0 V

•

Moisture Sensitivity Level: Pb = 1; Pb−Free = 3

For Additional Information, see Application Note

AND8003/D

Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

Transistor Count = 212 devices

Pb−Free Packages are Available*

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

MARKING DIAGRAM*

http://onsemi.com

MC100E310FNG

AWLYYWW

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Publication Order Number:

1 28

FN SUFFIX

CASE 776

PLCC−28

MC100E310/D

Related parts for MC100E310FNR2

MC100E310FNR2 Summary of contents

Page 1

... Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 January, 2009 − Rev switching reference voltage. ...

Page 2

CCO CLK_SEL 28 CLKa Pinout: 28−Lead PLCC (Top View) CLKa CLKb CLKb NC Q7 ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature Range A T Storage Temperature Range ...

Page 4

Table 4. 100E SERIES PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended) IL ...

Page 5

... EE 8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1−12) of the ON Semiconductor High Performance ECL Data Book (DL140/D). 9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. ...

Page 6

... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100E310FN MC100E310FNG MC100E310FNR2 MC100E310FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 7

0.010 (0.250 NOTES: 1. DATUMS ‐L‐, ‐M‐, AND ‐N‐ DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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