CY22150KFZXC Cypress Semiconductor Corp, CY22150KFZXC Datasheet - Page 7

• Manufacturer Part Number: CY22150KFZXC
• Description: IC CLOCK GEN PROG FLASH 16-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY22150KFZXC

• Number Of Circuits: 1
• Package / Case: 16-TSSOP
• Pll: Yes
• Input: Crystal
• Output: Clock
• Ratio - Input:output: 1:6
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 133 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 0.08 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Number Of Elements: 1
• Supply Current: 45mA
• Pll Input Freq (min): 1MHz
• Pll Input Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY30700 - KIT PROG FOR CY22150
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 11. Register 40H Change Pump Bit Settings
Although using the above table guarantees stability, it is recom-
mended to use the Print Preview function in CyClocksRT to
determine the correct charge pump settings for optimal jitter
performance.
PLL stability cannot be guaranteed for values below 16 and
above 1023. If values above 1023 are needed, use CyClocksRT
to determine the best charge pump setting.
Clock Output Settings: CLKSRC – Clock Output
Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)],
[46H(7..6)]
CLKOE – Clock Output Enable Control [09H(5..0)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint switch
matrix defines which source is attached to each individual clock
output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H.
The remainder of register 46H(5:0) must be written with the
values stated in the register table when writing register values
46H(7:6).
In addition, each clock output has individual CLKOE control, set
by register 09H(5..0).
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed
Table 12. Clock Output Setting
Table 13. Clock Output Register Setting
Document #: 38-07104 Rev. *I
CLKSRC2
Address
Address
40H
44H
45H
46H
0
0
0
0
1
1
1
1
to
CLKSRC2 for
CLKSRC0 for
CLKSRC1 for
CLKSRC1
LCLK1
LCLK3
CLK6
be
D7
0
0
1
1
0
0
1
1
D7
1
rising
CLKSRC1 for
CLKSRC2 for
CLKSRC0 for
CLKSRC0
LCLK1
LCLK4
CLK6
edge
0
1
0
1
0
1
0
1
D6
D6
1
phase-aligned
Reference input.
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4
to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4
to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
Reserved – do not use.
CLKSRC0 for
CLKSRC1 for
LCLK1
LCLK4
D5
D5
1
0
CLKSRC2 for
CLKSRC0 for
with
Pump(2)
LCLK2
LCLK4
D4
D4
1
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
guaranteed
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in
The output swing of LCLK1 through LCLK4 is set by V
output swing of CLK5 and CLK6 is set by V
Test, Reserved, and Blank Registers
Writing to any of the following registers causes the part to exhibit
abnormal behavior, as follows.
[00H to 08H]
[0AH to 0BH]
[0DH to 11H]
[14H to 3FH]
[43H]
[48H to FFH]
CLKSRC1 for
CLKSRC2 for
Definition and Notes
Pump(1)
LCLK2
CLK5
D3
D3
1
to
to
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved.
be
be
CLKSRC0 for
CLKSRC1 for
Pump(0)
LCLK2
CLK5
rising
rising
D2
D2
1
edge
edge
CLKSRC2 for
CLKSRC0 for
LCLK3
CLK5
PB(9)
Table 14
D1
D1
1
phase-aligned
phase-aligned
DD
.
CY22150
on page 8.
CLKSRC1 for
CLKSRC2 for
Page 7 of 16
LCLK3
CLK6
PB(8)
DDL
D0
D0
1
. The
with
with
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