LMX2531LQ2080E/NOPB National Semiconductor, LMX2531LQ2080E/NOPB Datasheet - Page 19

• Manufacturer Part Number: LMX2531LQ2080E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2531LQ2080E/NOPB

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 2.274GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.8 V ~ 3.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 2.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2531LQ2080ETR

delta sigma engine is dithering. Dithering is often effective in
reducing these additional spurious tones, but can add phase
noise in some situations. The third degree of freedom is the
way that the fraction is expressed. For example, 1/10 can be
expressed as 100000/1000000. Expressing the fraction in
higher order terms sometimes improves the performance,
particularly when dithering is used. In conclusion, there are
some guidelines to getting the optimum choice of settings, but
these optimum settings are application specific. Refer to ap-
plication note 1879 for a much more detailed discussion on
fractional PLLs and fractional spurs..
1.5 PARTIALLY INTEGRATED LOOP FILTER
The LMX2531 integrates the third pole (formed by R3 and C3)
and fourth pole (formed by R4 and C4) of the loop filter. The
values for C3, C4, R3, and R4 can also be programmed in-
dependently through the MICROWIRE interface and also R3
and R4 can be changed during FastLock ™ , for minimum lock
time. The larger the values of these components, the stronger
the attenuation of the internal loop filter. The maximum atten-
uation can be achieved by setting R3=R4=40 kΩ and
C3=C4=100 pF while the minimum attenuation is achieved by
disabling the loop filter by setting EN_LPFLTR (R6[15]) to ze-
ro. Note that when the internal loop filter is disabled, there is
still a small amount of input capacitance on front of the VCO
on the order of 200 pF.
Since that the internal loop filter is on-chip, it is more effective
at reducing certain spurs than the external loop filter. The
higher order poles formed by the integrated loop filter are also
helpful for attenuating noise due to the delta-sigma modula-
tor. This noise produced by the delta-sigma modulator is
outside the loop bandwidth and dependent on the modulator
order. Although setting the filtering for maximum attenuation
gives the best filtering, it puts increased restrictions on how
wide the loop bandwidth of the system can be, which corre-
sponds to the case where the shunt loop filter capacitor, C1,
is zero. Increasing the charge pump current and/or the phase
detector frequency increases the maximum attainable loop
bandwidth when designing with the integrated filter. It is rec-
ommended to set the internal loop filter as high as possible
without restricting the loop bandwidth of the system more than
desired. If some setting between the minimum and maximum
value is desired, it is preferable to reduce the resistor values
before reducing the capacitor values since this will reduce the
thermal noise contribution of the loop filter resistors. For de-
sign tools and more information on partially integrated loop
filters, go to www.national.com/wireless.
1.6 LOW NOISE, FULLY INTEGRATED VCO
The LMX2531 includes a fully integrated VCO, including the
inductors. For optimum phase noise performance, this VCO
has frequency and phase noise calibration algorithms. The
frequency calibration algorithm is necessary because the
19
VCO internally divides up the frequency range into several
bands, in order to achieve a lower tuning gain, and therefore
better phase noise performance. The frequency calibration
routine is activated any time that the R0 register is pro-
grammed. There are several bits including LOCKMODE and
XTLSEL that need to be set properly for this calibration to be
performed in a reliable fashion. If the temperature shifts con-
siderably and the R0 register is not programmed, then it can
not drift more than the maximum allowable drift for continuous
lock, ΔT
The phase noise calibration algorithm is necessary in order
to achieve the lowest possible phase noise. Each version of
the LMX2531, the VCO_ACI_SEL bit (R6[19:16]) needs to be
set to the correct value to ensure the best possible phase
noise.
The gain of the VCO can change considerably over frequen-
cy. It is lowest at the minimum frequency and highest at the
maximum frequency. This range is specified in the electrical
specifications section of the datasheet. When designing the
loop filter, the following method is recommended to determine
what VCO gain to design to. First, take the geometric mean
of the minimum and maximum frequencies that are to be
used. Then use a linear approximation to extrapolate the VCO
gain.
LMX2531LQ2080E PLL to tune from 2100 to 2150 MHz. The
geometric mean of these frequencies is sqrt(2100 × 2150)
MHz = 2125 MHz. The VCO gain is specified as 9 MHz/V at
1904 MHz and 20 MHz/V at 2274 MHz. Over this range of 370
MHz, the VCO gain changes 11 MHz/V. So at 2125 MHz, the
VCO gain would be approximately 9 + (2125-1904)* 11/370
= 15.6 MHz/V. Although the VCO gain can change from part
to part, this variation is small compared to how much the VCO
gain can change over frequency.
The VCO frequency is related to the other frequencies and
divider values as follows:
1.7 PROGRAMMABLE VCO DIVIDER
All options of the LMX2531 offer the option of dividing the
VCO output by two to get half of the VCO frequency at the
Fout pin. The channel spacing at the Fout pin is also divided
by two as well. Because this divide by two is outside feedback
path between the VCO and the PLL, enabling does require
one to change the N divider, R divider, or loop filter values.
When this divider is enabled, there will be some far-out phase
noise contribution to the VCO noise. Note that the R0 register
should be reprogrammed the first time after the DIV2 bit is
enabled or disabled for optimal phase noise performance.
The frequency at the Fout pin is related to the VCO frequency
and divider value, D, as follows:
CL
Suppose
, or else the VCO is not guaranteed to stay in lock.
f
VCO
= f
the
PD
f
Fout
× N = f
= f
application
VCO
OSCin
/ D
× N / R
requires
www.national.com
the