MK1704ATR IDT, Integrated Device Technology Inc, MK1704ATR Datasheet - Page 2

• Manufacturer Part Number: MK1704ATR
• Description: IC CLK GENERATOR LOW EMI 8-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Generatorr

Specifications of MK1704ATR

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: No/No
• Frequency - Max: 140MHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Frequency-max: 140MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Assignment
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 trace (a commonly
used trace impedance), place a 33 resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20 .
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
IDT™ LOW EMI CLOCK GENERATOR
MK1704A
LOW EMI CLOCK GENERATOR
ICLK
GND
VDD
CLK
Number
Pin
1
2
3
4
5
6
7
8
8 pin (150 mil) SOIC
1
2
3
4
Name
ICLK
GND
VDD
CLK
LEE
Pin
NC
S1
S0
8
7
6
5
Output
Power
Power
Type
Input
Input
Input
Pin
NC
S0
S1
LEE
XI
-
Connect to a clock input as shown in table above.
Connect to +3.3V or +5V.
Connect to ground.
Clock output equal to input frequency.
Low EMI enable. Turns on the spread spectrum when high. Internal pull-up.
Frequency select 1 input. Selects input/output clock range per table above.
Internal pull-up.
Frequency select 0 input. Selects input/output clock range per table above.
Internal pull-up.
No connect. Do not connect anything to this pin.
2
Output Clock Selection Table
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI the 33 series termination resistor, if
needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
S1 S0
0
0
1
1
0
1
0
1
Input
Min.
60
60
30
40
Pin Description
Input
Nom.
135
80
40
65
Input
Max. Mult.
140
120
100
60
x1
x1
x1
x1
MK1704A
+0.5, -1.5%
+0.5, -1.5%
+0.5, -1.5%
Down 2.5%
vs. CLK
spread
Freq.
REV G 051310
SSCG