ICS951411BGLF IDT, Integrated Device Technology Inc, ICS951411BGLF Datasheet - Page 11

• Manufacturer Part Number: ICS951411BGLF
• Description: IC SYSTEM CLOCK CHIP P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of ICS951411BGLF

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 951411BGLF

Absolute Max
0891E—03/07/05
T
1
2
3
ppm frequency accuracy on PLL outputs.
Electrical Characteristics - Input/Supply/Common Output Parameters
Tambient
Low-level Output Voltage
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
ESD prot
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
Symbol
A
VDD_In
VDD_A
Tcase
Modulation Frequency
Clock/Data Rise Time
Low Threshold Input-
Low Threshold Input-
Clock/Data Fall Time
= 0 - 70°C; Supply Voltage V
Powerdown Current
Input High Voltage
Input High Current
Ts
Input Low Voltage
Operating Current
Input Capacitance
Input Low Current
Current sinking at
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
PARAMETER
SCLK/SDATA
SCLK/SDATA
High Voltage
Low Voltage
Tdrive_PD#
V
Trise_Pd#
Tfall_Pd#
OL
Integrated
Circuit
Systems, Inc.
= 0.4 V
3.3V Logic Input Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Storage Temperature
Input ESD protection
human body model
Case Temperature
Parameter
SYMBOL
I
I
I
DD3.3OP
V
V
DD3.3PD
T
PULLUP
C
T
T
C
V
V
L
C
V
IH_FS
V
I
I
IL_FS
STAB
I
RI2C
FI2C
F
OUT
IL1
IL2
IH
pin
INX
DD
DD
OL
IH
IL
IN
i
= 3.3 V +/-5%
V
IN
assertion of PD# to 1st clock
V
all differential pairs tri-stated
From V
IN
= 0 V; Inputs with no pull-up
CPU output enable after
Output pin capacitance
Triangular Modulation
= 0 V; Inputs with pull-up
(Min VIH + 0.15) to
(Max VIL - 0.15) to
all diff pairs driven
PD# de-assertion
all outputs driven
(Min VIH + 0.15)
(Max VIL - 0.15)
PD# rise time of
PD# fall time of
CONDITIONS
X1 & X2 pins
Logic Inputs
DD
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V
GND - 0.5
V
@ I
resistors
resistors
DD
IN
Power-Up or de-
2000
Min
-65
= 3.3 V
PULLUP
0
= V
DD
V
V
DD
DD
11
Max
150
115
+ 0.5V
+ 0.5V
70
V
V
SS
SS
-200
MIN
0.7
2.7
30
-5
-5
2
4
- 0.3
- 0.3
Units
°C
°C
°
V
V
V
C
14.31818
TYP
V
V
DD
DD
MAX
1000
0.35
400
300
300
0.8
1.8
5.5
0.4
70
12
33
5
7
5
6
5
5
5
+ 0.3
+ 0.3
UNITS Notes
MHz
kHz
mA
mA
mA
mA
ms
uA
uA
uA
nH
pF
pF
pF
us
ns
ns
ns
ns
V
V
V
V
V
V
ICS951411
1,2
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
2
1
1
1
1
1